Lines Matching refs:x1
39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1
59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1
61 #define QIB_7220_Control_Reserved_RMASK 0x1
63 #define QIB_7220_Control_TxLatency_RMASK 0x1
65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1
67 #define QIB_7220_Control_LinkEn_RMASK 0x1
68 #define QIB_7220_Control_FreezeMode_LSB 0x1
69 #define QIB_7220_Control_FreezeMode_RMASK 0x1
71 #define QIB_7220_Control_SyncReset_RMASK 0x1
87 #define QIB_7220_IntMask_SDmaIntMask_RMASK 0x1
89 #define QIB_7220_IntMask_SDmaDisabledMasked_RMASK 0x1
93 #define QIB_7220_IntMask_RcvUrg16IntMask_RMASK 0x1
95 #define QIB_7220_IntMask_RcvUrg15IntMask_RMASK 0x1
97 #define QIB_7220_IntMask_RcvUrg14IntMask_RMASK 0x1
99 #define QIB_7220_IntMask_RcvUrg13IntMask_RMASK 0x1
101 #define QIB_7220_IntMask_RcvUrg12IntMask_RMASK 0x1
103 #define QIB_7220_IntMask_RcvUrg11IntMask_RMASK 0x1
105 #define QIB_7220_IntMask_RcvUrg10IntMask_RMASK 0x1
107 #define QIB_7220_IntMask_RcvUrg9IntMask_RMASK 0x1
109 #define QIB_7220_IntMask_RcvUrg8IntMask_RMASK 0x1
111 #define QIB_7220_IntMask_RcvUrg7IntMask_RMASK 0x1
113 #define QIB_7220_IntMask_RcvUrg6IntMask_RMASK 0x1
115 #define QIB_7220_IntMask_RcvUrg5IntMask_RMASK 0x1
117 #define QIB_7220_IntMask_RcvUrg4IntMask_RMASK 0x1
119 #define QIB_7220_IntMask_RcvUrg3IntMask_RMASK 0x1
121 #define QIB_7220_IntMask_RcvUrg2IntMask_RMASK 0x1
123 #define QIB_7220_IntMask_RcvUrg1IntMask_RMASK 0x1
125 #define QIB_7220_IntMask_RcvUrg0IntMask_RMASK 0x1
127 #define QIB_7220_IntMask_ErrorIntMask_RMASK 0x1
129 #define QIB_7220_IntMask_PioSetIntMask_RMASK 0x1
131 #define QIB_7220_IntMask_PioBufAvailIntMask_RMASK 0x1
133 #define QIB_7220_IntMask_assertGPIOIntMask_RMASK 0x1
135 #define QIB_7220_IntMask_IBSerdesTrimDoneIntMask_RMASK 0x1
137 #define QIB_7220_IntMask_JIntMask_RMASK 0x1
141 #define QIB_7220_IntMask_RcvAvail16IntMask_RMASK 0x1
143 #define QIB_7220_IntMask_RcvAvail15IntMask_RMASK 0x1
145 #define QIB_7220_IntMask_RcvAvail14IntMask_RMASK 0x1
147 #define QIB_7220_IntMask_RcvAvail13IntMask_RMASK 0x1
149 #define QIB_7220_IntMask_RcvAvail12IntMask_RMASK 0x1
151 #define QIB_7220_IntMask_RcvAvail11IntMask_RMASK 0x1
153 #define QIB_7220_IntMask_RcvAvail10IntMask_RMASK 0x1
155 #define QIB_7220_IntMask_RcvAvail9IntMask_RMASK 0x1
157 #define QIB_7220_IntMask_RcvAvail8IntMask_RMASK 0x1
159 #define QIB_7220_IntMask_RcvAvail7IntMask_RMASK 0x1
161 #define QIB_7220_IntMask_RcvAvail6IntMask_RMASK 0x1
163 #define QIB_7220_IntMask_RcvAvail5IntMask_RMASK 0x1
165 #define QIB_7220_IntMask_RcvAvail4IntMask_RMASK 0x1
167 #define QIB_7220_IntMask_RcvAvail3IntMask_RMASK 0x1
169 #define QIB_7220_IntMask_RcvAvail2IntMask_RMASK 0x1
170 #define QIB_7220_IntMask_RcvAvail1IntMask_LSB 0x1
171 #define QIB_7220_IntMask_RcvAvail1IntMask_RMASK 0x1
173 #define QIB_7220_IntMask_RcvAvail0IntMask_RMASK 0x1
177 #define QIB_7220_IntStatus_SDmaInt_RMASK 0x1
179 #define QIB_7220_IntStatus_SDmaDisabled_RMASK 0x1
183 #define QIB_7220_IntStatus_RcvUrg16_RMASK 0x1
185 #define QIB_7220_IntStatus_RcvUrg15_RMASK 0x1
187 #define QIB_7220_IntStatus_RcvUrg14_RMASK 0x1
189 #define QIB_7220_IntStatus_RcvUrg13_RMASK 0x1
191 #define QIB_7220_IntStatus_RcvUrg12_RMASK 0x1
193 #define QIB_7220_IntStatus_RcvUrg11_RMASK 0x1
195 #define QIB_7220_IntStatus_RcvUrg10_RMASK 0x1
197 #define QIB_7220_IntStatus_RcvUrg9_RMASK 0x1
199 #define QIB_7220_IntStatus_RcvUrg8_RMASK 0x1
201 #define QIB_7220_IntStatus_RcvUrg7_RMASK 0x1
203 #define QIB_7220_IntStatus_RcvUrg6_RMASK 0x1
205 #define QIB_7220_IntStatus_RcvUrg5_RMASK 0x1
207 #define QIB_7220_IntStatus_RcvUrg4_RMASK 0x1
209 #define QIB_7220_IntStatus_RcvUrg3_RMASK 0x1
211 #define QIB_7220_IntStatus_RcvUrg2_RMASK 0x1
213 #define QIB_7220_IntStatus_RcvUrg1_RMASK 0x1
215 #define QIB_7220_IntStatus_RcvUrg0_RMASK 0x1
217 #define QIB_7220_IntStatus_Error_RMASK 0x1
219 #define QIB_7220_IntStatus_PioSent_RMASK 0x1
221 #define QIB_7220_IntStatus_PioBufAvail_RMASK 0x1
223 #define QIB_7220_IntStatus_assertGPIO_RMASK 0x1
225 #define QIB_7220_IntStatus_IBSerdesTrimDone_RMASK 0x1
227 #define QIB_7220_IntStatus_JInt_RMASK 0x1
231 #define QIB_7220_IntStatus_RcvAvail16_RMASK 0x1
233 #define QIB_7220_IntStatus_RcvAvail15_RMASK 0x1
235 #define QIB_7220_IntStatus_RcvAvail14_RMASK 0x1
237 #define QIB_7220_IntStatus_RcvAvail13_RMASK 0x1
239 #define QIB_7220_IntStatus_RcvAvail12_RMASK 0x1
241 #define QIB_7220_IntStatus_RcvAvail11_RMASK 0x1
243 #define QIB_7220_IntStatus_RcvAvail10_RMASK 0x1
245 #define QIB_7220_IntStatus_RcvAvail9_RMASK 0x1
247 #define QIB_7220_IntStatus_RcvAvail8_RMASK 0x1
249 #define QIB_7220_IntStatus_RcvAvail7_RMASK 0x1
251 #define QIB_7220_IntStatus_RcvAvail6_RMASK 0x1
253 #define QIB_7220_IntStatus_RcvAvail5_RMASK 0x1
255 #define QIB_7220_IntStatus_RcvAvail4_RMASK 0x1
257 #define QIB_7220_IntStatus_RcvAvail3_RMASK 0x1
259 #define QIB_7220_IntStatus_RcvAvail2_RMASK 0x1
260 #define QIB_7220_IntStatus_RcvAvail1_LSB 0x1
261 #define QIB_7220_IntStatus_RcvAvail1_RMASK 0x1
263 #define QIB_7220_IntStatus_RcvAvail0_RMASK 0x1
267 #define QIB_7220_IntClear_SDmaIntClear_RMASK 0x1
269 #define QIB_7220_IntClear_SDmaDisabledClear_RMASK 0x1
273 #define QIB_7220_IntClear_RcvUrg16IntClear_RMASK 0x1
275 #define QIB_7220_IntClear_RcvUrg15IntClear_RMASK 0x1
277 #define QIB_7220_IntClear_RcvUrg14IntClear_RMASK 0x1
279 #define QIB_7220_IntClear_RcvUrg13IntClear_RMASK 0x1
281 #define QIB_7220_IntClear_RcvUrg12IntClear_RMASK 0x1
283 #define QIB_7220_IntClear_RcvUrg11IntClear_RMASK 0x1
285 #define QIB_7220_IntClear_RcvUrg10IntClear_RMASK 0x1
287 #define QIB_7220_IntClear_RcvUrg9IntClear_RMASK 0x1
289 #define QIB_7220_IntClear_RcvUrg8IntClear_RMASK 0x1
291 #define QIB_7220_IntClear_RcvUrg7IntClear_RMASK 0x1
293 #define QIB_7220_IntClear_RcvUrg6IntClear_RMASK 0x1
295 #define QIB_7220_IntClear_RcvUrg5IntClear_RMASK 0x1
297 #define QIB_7220_IntClear_RcvUrg4IntClear_RMASK 0x1
299 #define QIB_7220_IntClear_RcvUrg3IntClear_RMASK 0x1
301 #define QIB_7220_IntClear_RcvUrg2IntClear_RMASK 0x1
303 #define QIB_7220_IntClear_RcvUrg1IntClear_RMASK 0x1
305 #define QIB_7220_IntClear_RcvUrg0IntClear_RMASK 0x1
307 #define QIB_7220_IntClear_ErrorIntClear_RMASK 0x1
309 #define QIB_7220_IntClear_PioSetIntClear_RMASK 0x1
311 #define QIB_7220_IntClear_PioBufAvailIntClear_RMASK 0x1
313 #define QIB_7220_IntClear_assertGPIOIntClear_RMASK 0x1
315 #define QIB_7220_IntClear_IBSerdesTrimDoneClear_RMASK 0x1
317 #define QIB_7220_IntClear_JIntClear_RMASK 0x1
321 #define QIB_7220_IntClear_RcvAvail16IntClear_RMASK 0x1
323 #define QIB_7220_IntClear_RcvAvail15IntClear_RMASK 0x1
325 #define QIB_7220_IntClear_RcvAvail14IntClear_RMASK 0x1
327 #define QIB_7220_IntClear_RcvAvail13IntClear_RMASK 0x1
329 #define QIB_7220_IntClear_RcvAvail12IntClear_RMASK 0x1
331 #define QIB_7220_IntClear_RcvAvail11IntClear_RMASK 0x1
333 #define QIB_7220_IntClear_RcvAvail10IntClear_RMASK 0x1
335 #define QIB_7220_IntClear_RcvAvail9IntClear_RMASK 0x1
337 #define QIB_7220_IntClear_RcvAvail8IntClear_RMASK 0x1
339 #define QIB_7220_IntClear_RcvAvail7IntClear_RMASK 0x1
341 #define QIB_7220_IntClear_RcvAvail6IntClear_RMASK 0x1
343 #define QIB_7220_IntClear_RcvAvail5IntClear_RMASK 0x1
345 #define QIB_7220_IntClear_RcvAvail4IntClear_RMASK 0x1
347 #define QIB_7220_IntClear_RcvAvail3IntClear_RMASK 0x1
349 #define QIB_7220_IntClear_RcvAvail2IntClear_RMASK 0x1
350 #define QIB_7220_IntClear_RcvAvail1IntClear_LSB 0x1
351 #define QIB_7220_IntClear_RcvAvail1IntClear_RMASK 0x1
353 #define QIB_7220_IntClear_RcvAvail0IntClear_RMASK 0x1
359 #define QIB_7220_ErrMask_InvalidEEPCmdMask_RMASK 0x1
361 #define QIB_7220_ErrMask_SDmaDescAddrMisalignErrMask_RMASK 0x1
363 #define QIB_7220_ErrMask_HardwareErrMask_RMASK 0x1
365 #define QIB_7220_ErrMask_ResetNegatedMask_RMASK 0x1
367 #define QIB_7220_ErrMask_InvalidAddrErrMask_RMASK 0x1
369 #define QIB_7220_ErrMask_IBStatusChangedMask_RMASK 0x1
371 #define QIB_7220_ErrMask_SDmaUnexpDataErrMask_RMASK 0x1
373 #define QIB_7220_ErrMask_SDmaMissingDwErrMask_RMASK 0x1
375 #define QIB_7220_ErrMask_SDmaDwEnErrMask_RMASK 0x1
377 #define QIB_7220_ErrMask_SDmaRpyTagErrMask_RMASK 0x1
379 #define QIB_7220_ErrMask_SDma1stDescErrMask_RMASK 0x1
381 #define QIB_7220_ErrMask_SDmaBaseErrMask_RMASK 0x1
383 #define QIB_7220_ErrMask_SDmaTailOutOfBoundErrMask_RMASK 0x1
385 #define QIB_7220_ErrMask_SDmaOutOfBoundErrMask_RMASK 0x1
387 #define QIB_7220_ErrMask_SDmaGenMismatchErrMask_RMASK 0x1
389 #define QIB_7220_ErrMask_SendBufMisuseErrMask_RMASK 0x1
391 #define QIB_7220_ErrMask_SendUnsupportedVLErrMask_RMASK 0x1
393 #define QIB_7220_ErrMask_SendUnexpectedPktNumErrMask_RMASK 0x1
395 #define QIB_7220_ErrMask_SendPioArmLaunchErrMask_RMASK 0x1
397 #define QIB_7220_ErrMask_SendDroppedDataPktErrMask_RMASK 0x1
399 #define QIB_7220_ErrMask_SendDroppedSmpPktErrMask_RMASK 0x1
401 #define QIB_7220_ErrMask_SendPktLenErrMask_RMASK 0x1
403 #define QIB_7220_ErrMask_SendUnderRunErrMask_RMASK 0x1
405 #define QIB_7220_ErrMask_SendMaxPktLenErrMask_RMASK 0x1
407 #define QIB_7220_ErrMask_SendMinPktLenErrMask_RMASK 0x1
409 #define QIB_7220_ErrMask_SDmaDisabledErrMask_RMASK 0x1
411 #define QIB_7220_ErrMask_SendSpecialTriggerErrMask_RMASK 0x1
415 #define QIB_7220_ErrMask_RcvIBLostLinkErrMask_RMASK 0x1
417 #define QIB_7220_ErrMask_RcvHdrErrMask_RMASK 0x1
419 #define QIB_7220_ErrMask_RcvHdrLenErrMask_RMASK 0x1
421 #define QIB_7220_ErrMask_RcvBadTidErrMask_RMASK 0x1
423 #define QIB_7220_ErrMask_RcvHdrFullErrMask_RMASK 0x1
425 #define QIB_7220_ErrMask_RcvEgrFullErrMask_RMASK 0x1
427 #define QIB_7220_ErrMask_RcvBadVersionErrMask_RMASK 0x1
429 #define QIB_7220_ErrMask_RcvIBFlowErrMask_RMASK 0x1
431 #define QIB_7220_ErrMask_RcvEBPErrMask_RMASK 0x1
433 #define QIB_7220_ErrMask_RcvUnsupportedVLErrMask_RMASK 0x1
435 #define QIB_7220_ErrMask_RcvUnexpectedCharErrMask_RMASK 0x1
437 #define QIB_7220_ErrMask_RcvShortPktLenErrMask_RMASK 0x1
439 #define QIB_7220_ErrMask_RcvLongPktLenErrMask_RMASK 0x1
441 #define QIB_7220_ErrMask_RcvMaxPktLenErrMask_RMASK 0x1
443 #define QIB_7220_ErrMask_RcvMinPktLenErrMask_RMASK 0x1
445 #define QIB_7220_ErrMask_RcvICRCErrMask_RMASK 0x1
446 #define QIB_7220_ErrMask_RcvVCRCErrMask_LSB 0x1
447 #define QIB_7220_ErrMask_RcvVCRCErrMask_RMASK 0x1
449 #define QIB_7220_ErrMask_RcvFormatErrMask_RMASK 0x1
455 #define QIB_7220_ErrStatus_InvalidEEPCmdErr_RMASK 0x1
457 #define QIB_7220_ErrStatus_SDmaDescAddrMisalignErr_RMASK 0x1
459 #define QIB_7220_ErrStatus_HardwareErr_RMASK 0x1
461 #define QIB_7220_ErrStatus_ResetNegated_RMASK 0x1
463 #define QIB_7220_ErrStatus_InvalidAddrErr_RMASK 0x1
465 #define QIB_7220_ErrStatus_IBStatusChanged_RMASK 0x1
467 #define QIB_7220_ErrStatus_SDmaUnexpDataErr_RMASK 0x1
469 #define QIB_7220_ErrStatus_SDmaMissingDwErr_RMASK 0x1
471 #define QIB_7220_ErrStatus_SDmaDwEnErr_RMASK 0x1
473 #define QIB_7220_ErrStatus_SDmaRpyTagErr_RMASK 0x1
475 #define QIB_7220_ErrStatus_SDma1stDescErr_RMASK 0x1
477 #define QIB_7220_ErrStatus_SDmaBaseErr_RMASK 0x1
479 #define QIB_7220_ErrStatus_SDmaTailOutOfBoundErr_RMASK 0x1
481 #define QIB_7220_ErrStatus_SDmaOutOfBoundErr_RMASK 0x1
483 #define QIB_7220_ErrStatus_SDmaGenMismatchErr_RMASK 0x1
485 #define QIB_7220_ErrStatus_SendBufMisuseErr_RMASK 0x1
487 #define QIB_7220_ErrStatus_SendUnsupportedVLErr_RMASK 0x1
489 #define QIB_7220_ErrStatus_SendUnexpectedPktNumErr_RMASK 0x1
491 #define QIB_7220_ErrStatus_SendPioArmLaunchErr_RMASK 0x1
493 #define QIB_7220_ErrStatus_SendDroppedDataPktErr_RMASK 0x1
495 #define QIB_7220_ErrStatus_SendDroppedSmpPktErr_RMASK 0x1
497 #define QIB_7220_ErrStatus_SendPktLenErr_RMASK 0x1
499 #define QIB_7220_ErrStatus_SendUnderRunErr_RMASK 0x1
501 #define QIB_7220_ErrStatus_SendMaxPktLenErr_RMASK 0x1
503 #define QIB_7220_ErrStatus_SendMinPktLenErr_RMASK 0x1
505 #define QIB_7220_ErrStatus_SDmaDisabledErr_RMASK 0x1
507 #define QIB_7220_ErrStatus_SendSpecialTriggerErr_RMASK 0x1
511 #define QIB_7220_ErrStatus_RcvIBLostLinkErr_RMASK 0x1
513 #define QIB_7220_ErrStatus_RcvHdrErr_RMASK 0x1
515 #define QIB_7220_ErrStatus_RcvHdrLenErr_RMASK 0x1
517 #define QIB_7220_ErrStatus_RcvBadTidErr_RMASK 0x1
519 #define QIB_7220_ErrStatus_RcvHdrFullErr_RMASK 0x1
521 #define QIB_7220_ErrStatus_RcvEgrFullErr_RMASK 0x1
523 #define QIB_7220_ErrStatus_RcvBadVersionErr_RMASK 0x1
525 #define QIB_7220_ErrStatus_RcvIBFlowErr_RMASK 0x1
527 #define QIB_7220_ErrStatus_RcvEBPErr_RMASK 0x1
529 #define QIB_7220_ErrStatus_RcvUnsupportedVLErr_RMASK 0x1
531 #define QIB_7220_ErrStatus_RcvUnexpectedCharErr_RMASK 0x1
533 #define QIB_7220_ErrStatus_RcvShortPktLenErr_RMASK 0x1
535 #define QIB_7220_ErrStatus_RcvLongPktLenErr_RMASK 0x1
537 #define QIB_7220_ErrStatus_RcvMaxPktLenErr_RMASK 0x1
539 #define QIB_7220_ErrStatus_RcvMinPktLenErr_RMASK 0x1
541 #define QIB_7220_ErrStatus_RcvICRCErr_RMASK 0x1
542 #define QIB_7220_ErrStatus_RcvVCRCErr_LSB 0x1
543 #define QIB_7220_ErrStatus_RcvVCRCErr_RMASK 0x1
545 #define QIB_7220_ErrStatus_RcvFormatErr_RMASK 0x1
551 #define QIB_7220_ErrClear_InvalidEEPCmdErrClear_RMASK 0x1
553 #define QIB_7220_ErrClear_SDmaDescAddrMisalignErrClear_RMASK 0x1
555 #define QIB_7220_ErrClear_HardwareErrClear_RMASK 0x1
557 #define QIB_7220_ErrClear_ResetNegatedClear_RMASK 0x1
559 #define QIB_7220_ErrClear_InvalidAddrErrClear_RMASK 0x1
561 #define QIB_7220_ErrClear_IBStatusChangedClear_RMASK 0x1
563 #define QIB_7220_ErrClear_SDmaUnexpDataErrClear_RMASK 0x1
565 #define QIB_7220_ErrClear_SDmaMissingDwErrClear_RMASK 0x1
567 #define QIB_7220_ErrClear_SDmaDwEnErrClear_RMASK 0x1
569 #define QIB_7220_ErrClear_SDmaRpyTagErrClear_RMASK 0x1
571 #define QIB_7220_ErrClear_SDma1stDescErrClear_RMASK 0x1
573 #define QIB_7220_ErrClear_SDmaBaseErrClear_RMASK 0x1
575 #define QIB_7220_ErrClear_SDmaTailOutOfBoundErrClear_RMASK 0x1
577 #define QIB_7220_ErrClear_SDmaOutOfBoundErrClear_RMASK 0x1
579 #define QIB_7220_ErrClear_SDmaGenMismatchErrClear_RMASK 0x1
581 #define QIB_7220_ErrClear_SendBufMisuseErrClear_RMASK 0x1
583 #define QIB_7220_ErrClear_SendUnsupportedVLErrClear_RMASK 0x1
585 #define QIB_7220_ErrClear_SendUnexpectedPktNumErrClear_RMASK 0x1
587 #define QIB_7220_ErrClear_SendPioArmLaunchErrClear_RMASK 0x1
589 #define QIB_7220_ErrClear_SendDroppedDataPktErrClear_RMASK 0x1
591 #define QIB_7220_ErrClear_SendDroppedSmpPktErrClear_RMASK 0x1
593 #define QIB_7220_ErrClear_SendPktLenErrClear_RMASK 0x1
595 #define QIB_7220_ErrClear_SendUnderRunErrClear_RMASK 0x1
597 #define QIB_7220_ErrClear_SendMaxPktLenErrClear_RMASK 0x1
599 #define QIB_7220_ErrClear_SendMinPktLenErrClear_RMASK 0x1
601 #define QIB_7220_ErrClear_SDmaDisabledErrClear_RMASK 0x1
603 #define QIB_7220_ErrClear_SendSpecialTriggerErrClear_RMASK 0x1
607 #define QIB_7220_ErrClear_RcvIBLostLinkErrClear_RMASK 0x1
609 #define QIB_7220_ErrClear_RcvHdrErrClear_RMASK 0x1
611 #define QIB_7220_ErrClear_RcvHdrLenErrClear_RMASK 0x1
613 #define QIB_7220_ErrClear_RcvBadTidErrClear_RMASK 0x1
615 #define QIB_7220_ErrClear_RcvHdrFullErrClear_RMASK 0x1
617 #define QIB_7220_ErrClear_RcvEgrFullErrClear_RMASK 0x1
619 #define QIB_7220_ErrClear_RcvBadVersionErrClear_RMASK 0x1
621 #define QIB_7220_ErrClear_RcvIBFlowErrClear_RMASK 0x1
623 #define QIB_7220_ErrClear_RcvEBPErrClear_RMASK 0x1
625 #define QIB_7220_ErrClear_RcvUnsupportedVLErrClear_RMASK 0x1
627 #define QIB_7220_ErrClear_RcvUnexpectedCharErrClear_RMASK 0x1
629 #define QIB_7220_ErrClear_RcvShortPktLenErrClear_RMASK 0x1
631 #define QIB_7220_ErrClear_RcvLongPktLenErrClear_RMASK 0x1
633 #define QIB_7220_ErrClear_RcvMaxPktLenErrClear_RMASK 0x1
635 #define QIB_7220_ErrClear_RcvMinPktLenErrClear_RMASK 0x1
637 #define QIB_7220_ErrClear_RcvICRCErrClear_RMASK 0x1
638 #define QIB_7220_ErrClear_RcvVCRCErrClear_LSB 0x1
639 #define QIB_7220_ErrClear_RcvVCRCErrClear_RMASK 0x1
641 #define QIB_7220_ErrClear_RcvFormatErrClear_RMASK 0x1
645 #define QIB_7220_HwErrMask_IBCBusFromSPCParityErrMask_RMASK 0x1
647 #define QIB_7220_HwErrMask_IBCBusToSPCParityErrMask_RMASK 0x1
649 #define QIB_7220_HwErrMask_Clk_uC_PLLNotLockedMask_RMASK 0x1
651 #define QIB_7220_HwErrMask_IBSerdesPClkNotDetectMask_RMASK 0x1
653 #define QIB_7220_HwErrMask_PCIESerdesQ3PClkNotDetectMask_RMASK 0x1
655 #define QIB_7220_HwErrMask_PCIESerdesQ2PClkNotDetectMask_RMASK 0x1
657 #define QIB_7220_HwErrMask_PCIESerdesQ1PClkNotDetectMask_RMASK 0x1
659 #define QIB_7220_HwErrMask_PCIESerdesQ0PClkNotDetectMask_RMASK 0x1
661 #define QIB_7220_HwErrMask_Reserved_RMASK 0x1
663 #define QIB_7220_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1
671 #define QIB_7220_HwErrMask_DDSRXEQMemoryParityErrMask_RMASK 0x1
673 #define QIB_7220_HwErrMask_IB_uC_MemoryParityErrMask_RMASK 0x1
675 #define QIB_7220_HwErrMask_PCIEOct1_uC_MemoryParityErrMask_RMASK 0x1
677 #define QIB_7220_HwErrMask_PCIEOct0_uC_MemoryParityErrMask_RMASK 0x1
683 #define QIB_7220_HwErrMask_PcieCplTimeoutMask_RMASK 0x1
685 #define QIB_7220_HwErrMask_PoisonedTLPMask_RMASK 0x1
687 #define QIB_7220_HwErrMask_SDmaMemReadErrMask_RMASK 0x1
695 #define QIB_7220_HwErrStatus_IBCBusFromSPCParityErr_RMASK 0x1
697 #define QIB_7220_HwErrStatus_IBCBusToSPCParityErr_RMASK 0x1
699 #define QIB_7220_HwErrStatus_Clk_uC_PLLNotLocked_RMASK 0x1
701 #define QIB_7220_HwErrStatus_IBSerdesPClkNotDetect_RMASK 0x1
703 #define QIB_7220_HwErrStatus_PCIESerdesQ3PClkNotDetect_RMASK 0x1
705 #define QIB_7220_HwErrStatus_PCIESerdesQ2PClkNotDetect_RMASK 0x1
707 #define QIB_7220_HwErrStatus_PCIESerdesQ1PClkNotDetect_RMASK 0x1
709 #define QIB_7220_HwErrStatus_PCIESerdesQ0PClkNotDetect_RMASK 0x1
711 #define QIB_7220_HwErrStatus_Reserved_RMASK 0x1
713 #define QIB_7220_HwErrStatus_PowerOnBISTFailed_RMASK 0x1
721 #define QIB_7220_HwErrStatus_DDSRXEQMemoryParityErr_RMASK 0x1
723 #define QIB_7220_HwErrStatus_IB_uC_MemoryParityErr_RMASK 0x1
725 #define QIB_7220_HwErrStatus_PCIE_uC_Oct1MemoryParityErr_RMASK 0x1
727 #define QIB_7220_HwErrStatus_PCIE_uC_Oct0MemoryParityErr_RMASK 0x1
733 #define QIB_7220_HwErrStatus_PcieCplTimeout_RMASK 0x1
735 #define QIB_7220_HwErrStatus_PoisenedTLP_RMASK 0x1
737 #define QIB_7220_HwErrStatus_SDmaMemReadErr_RMASK 0x1
745 #define QIB_7220_HwErrClear_IBCBusFromSPCParityErrClear_RMASK 0x1
747 #define QIB_7220_HwErrClear_IBCBusToSPCparityErrClear_RMASK 0x1
749 #define QIB_7220_HwErrClear_Clk_uC_PLLNotLockedClear_RMASK 0x1
751 #define QIB_7220_HwErrClear_IBSerdesPClkNotDetectClear_RMASK 0x1
753 #define QIB_7220_HwErrClear_PCIESerdesQ3PClkNotDetectClear_RMASK 0x1
755 #define QIB_7220_HwErrClear_PCIESerdesQ2PClkNotDetectClear_RMASK 0x1
757 #define QIB_7220_HwErrClear_PCIESerdesQ1PClkNotDetectClear_RMASK 0x1
759 #define QIB_7220_HwErrClear_PCIESerdesQ0PClkNotDetectClear_RMASK 0x1
761 #define QIB_7220_HwErrClear_Reserved_RMASK 0x1
763 #define QIB_7220_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1
771 #define QIB_7220_HwErrClear_DDSRXEQMemoryParityErrClear_RMASK 0x1
773 #define QIB_7220_HwErrClear_IB_uC_MemoryParityErrClear_RMASK 0x1
775 #define QIB_7220_HwErrClear_PCIE_uC_Oct1MemoryParityErrClear_RMASK 0x1
777 #define QIB_7220_HwErrClear_PCIE_uC_Oct0MemoryParityErrClear_RMASK 0x1
783 #define QIB_7220_HwErrClear_PcieCplTimeoutClear_RMASK 0x1
785 #define QIB_7220_HwErrClear_PoisonedTLPClear_RMASK 0x1
787 #define QIB_7220_HwErrClear_SDmaMemReadErrClear_RMASK 0x1
795 #define QIB_7220_HwDiagCtrl_ForceIBCBusFromSPCParityErr_RMASK 0x1
797 #define QIB_7220_HwDiagCtrl_ForceIBCBusToSPCParityErr_RMASK 0x1
799 #define QIB_7220_HwDiagCtrl_CounterWrEnable_RMASK 0x1
801 #define QIB_7220_HwDiagCtrl_CounterDisable_RMASK 0x1
809 #define QIB_7220_HwDiagCtrl_ForceDDSRXEQMemoryParityErr_RMASK 0x1
811 #define QIB_7220_HwDiagCtrl_ForceIB_uC_MemoryParityErr_RMASK 0x1
813 #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct1MemoryParityErr_RMASK 0x1
815 #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct0MemoryParityErr_RMASK 0x1
817 #define QIB_7220_HwDiagCtrl_Reserved1_RMASK 0x1
829 #define QIB_7220_IBCStatus_TxCreditOk_RMASK 0x1
831 #define QIB_7220_IBCStatus_TxReady_RMASK 0x1
835 #define QIB_7220_IBCStatus_IBTxLaneReversed_RMASK 0x1
837 #define QIB_7220_IBCStatus_IBRxLaneReversed_RMASK 0x1
839 #define QIB_7220_IBCStatus_IB_SERDES_TRIM_DONE_RMASK 0x1
841 #define QIB_7220_IBCStatus_DDS_RXEQ_FAIL_RMASK 0x1
843 #define QIB_7220_IBCStatus_LinkWidthActive_RMASK 0x1
845 #define QIB_7220_IBCStatus_LinkSpeedActive_RMASK 0x1
853 #define QIB_7220_IBCCtrl_Loopback_RMASK 0x1
855 #define QIB_7220_IBCCtrl_LinkDownDefaultState_RMASK 0x1
883 #define QIB_7220_EXTStatus_MemBISTDisabled_RMASK 0x1
885 #define QIB_7220_EXTStatus_MemBISTEndTest_RMASK 0x1
897 #define QIB_7220_EXTCtrl_LEDPriPortGreenOn_RMASK 0x1
899 #define QIB_7220_EXTCtrl_LEDPriPortYellowOn_RMASK 0x1
900 #define QIB_7220_EXTCtrl_LEDGblOkGreenOn_LSB 0x1
901 #define QIB_7220_EXTCtrl_LEDGblOkGreenOn_RMASK 0x1
903 #define QIB_7220_EXTCtrl_LEDGblErrRedOff_RMASK 0x1
917 #define QIB_7220_RcvCtrl_RcvQPMapEnable_RMASK 0x1
921 #define QIB_7220_RcvCtrl_TailUpd_RMASK 0x1
923 #define QIB_7220_RcvCtrl_RcvPartitionKeyDisable_RMASK 0x1
979 #define QIB_7220_IBCDDRCtrl_HRTBT_REQ_RMASK 0x1
983 #define QIB_7220_IBCDDRCtrl_HRTBT_AUTO_RMASK 0x1
985 #define QIB_7220_IBCDDRCtrl_HRTBT_ENB_RMASK 0x1
989 #define QIB_7220_IBCDDRCtrl_SD_DDSV_RMASK 0x1
991 #define QIB_7220_IBCDDRCtrl_SD_ADD_ENB_RMASK 0x1
993 #define QIB_7220_IBCDDRCtrl_SD_RX_EQUAL_ENABLE_RMASK 0x1
995 #define QIB_7220_IBCDDRCtrl_IB_LANE_REV_SUPPORTED_RMASK 0x1
997 #define QIB_7220_IBCDDRCtrl_IB_POLARITY_REV_SUPP_RMASK 0x1
1001 #define QIB_7220_IBCDDRCtrl_SD_SPEED_QDR_RMASK 0x1
1003 #define QIB_7220_IBCDDRCtrl_SD_SPEED_DDR_RMASK 0x1
1005 #define QIB_7220_IBCDDRCtrl_SD_SPEED_SDR_RMASK 0x1
1006 #define QIB_7220_IBCDDRCtrl_SD_SPEED_LSB 0x1
1007 #define QIB_7220_IBCDDRCtrl_SD_SPEED_RMASK 0x1
1009 #define QIB_7220_IBCDDRCtrl_IB_ENHANCED_MODE_RMASK 0x1
1021 #define QIB_7220_IBCDDRStatus_heartbeat_timed_out_RMASK 0x1
1047 #define QIB_7220_IBNCModeCtrl_TSMEnable_ignore_TSM_on_rx_RMASK 0x1
1048 #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS2_LSB 0x1
1049 #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS2_RMASK 0x1
1051 #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS1_RMASK 0x1
1055 #define QIB_7220_SendCtrl_Disarm_RMASK 0x1
1065 #define QIB_7220_SendCtrl_SDmaHalt_RMASK 0x1
1067 #define QIB_7220_SendCtrl_SDmaEnable_RMASK 0x1
1069 #define QIB_7220_SendCtrl_SDmaSingleDescriptor_RMASK 0x1
1071 #define QIB_7220_SendCtrl_SDmaIntEnable_RMASK 0x1
1075 #define QIB_7220_SendCtrl_SSpecialTriggerEn_RMASK 0x1
1077 #define QIB_7220_SendCtrl_SPioEnable_RMASK 0x1
1079 #define QIB_7220_SendCtrl_SendBufAvailUpd_RMASK 0x1
1080 #define QIB_7220_SendCtrl_SendIntBufAvail_LSB 0x1
1081 #define QIB_7220_SendCtrl_SendIntBufAvail_RMASK 0x1
1083 #define QIB_7220_SendCtrl_Abort_RMASK 0x1
1168 #define QIB_7220_SendDmaStatus_ScoreBoardDrainInProg_RMASK 0x1
1170 #define QIB_7220_SendDmaStatus_AbortInProg_RMASK 0x1
1172 #define QIB_7220_SendDmaStatus_InternalSDmaEnable_RMASK 0x1
1180 #define QIB_7220_SendDmaStatus_ScbFull_RMASK 0x1
1182 #define QIB_7220_SendDmaStatus_ScbEmpty_RMASK 0x1
1184 #define QIB_7220_SendDmaStatus_ScbEntryValid_RMASK 0x1
1186 #define QIB_7220_SendDmaStatus_ScbFetchDescFlag_RMASK 0x1
1188 #define QIB_7220_SendDmaStatus_SplFifoReadyToGo_RMASK 0x1
1190 #define QIB_7220_SendDmaStatus_SplFifoDisarmed_RMASK 0x1
1192 #define QIB_7220_SendDmaStatus_SplFifoEmpty_RMASK 0x1
1194 #define QIB_7220_SendDmaStatus_SplFifoFull_RMASK 0x1
1218 #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_granted_RMASK 0x1
1219 #define QIB_7220_ibsd_epb_access_ctrl_Reserved_LSB 0x1
1222 #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_RMASK 0x1
1226 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_rdy_RMASK 0x1
1228 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_req_error_RMASK 0x1
1230 #define QIB_7220_ibsd_epb_transaction_reg_Reserved_RMASK 0x1
1232 #define QIB_7220_ibsd_epb_transaction_reg_mem_data_parity_RMASK 0x1
1234 #define QIB_7220_ibsd_epb_transaction_reg_Reserved1_RMASK 0x1
1238 #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_read_write_RMASK 0x1
1240 #define QIB_7220_ibsd_epb_transaction_reg_Reserved2_RMASK 0x1
1248 #define QIB_7220_XGXSCfg_sel_link_down_for_fctrl_lane_sync_reset_RMASK 0x1
1256 #define QIB_7220_XGXSCfg_xcv_reset_RMASK 0x1
1257 #define QIB_7220_XGXSCfg_Reserved2_LSB 0x1
1258 #define QIB_7220_XGXSCfg_Reserved2_RMASK 0x1
1260 #define QIB_7220_XGXSCfg_tx_rx_reset_RMASK 0x1
1266 #define QIB_7220_IBSerDesCtrl_INT_uC_RMASK 0x1
1274 #define QIB_7220_IBSerDesCtrl_TXOBPD_RMASK 0x1
1276 #define QIB_7220_IBSerDesCtrl_TWC_RMASK 0x1
1278 #define QIB_7220_IBSerDesCtrl_RXIDLE_RMASK 0x1
1280 #define QIB_7220_IBSerDesCtrl_RXINV_RMASK 0x1
1282 #define QIB_7220_IBSerDesCtrl_TXINV_RMASK 0x1
1289 #define QIB_7220_IBSerDesCtrl_Reserved2_LSB 0x1
1292 #define QIB_7220_IBSerDesCtrl_ResetIB_uC_Core_RMASK 0x1
1296 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_granted_RMASK 0x1
1299 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcieepb_star_en_LSB 0x1
1302 #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_RMASK 0x1
1306 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_rdy_RMASK 0x1
1308 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_req_error_RMASK 0x1
1310 #define QIB_7220_pciesd_epb_transaction_reg_Reserved_RMASK 0x1
1312 #define QIB_7220_pciesd_epb_transaction_reg_mem_data_parity_RMASK 0x1
1316 #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_read_write_RMASK 0x1
1318 #define QIB_7220_pciesd_epb_transaction_reg_Reserved1_RMASK 0x1