Searched refs:write_reg_dly (Results 1 - 2 of 2) sorted by relevance
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/mbx/ |
H A D | mbxfb.c | 45 #define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0) macro 272 write_reg_dly(gsctrl, GSCTRL); 277 write_reg_dly(gsadr, GSADR); 282 write_reg_dly((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) | 295 write_reg_dly((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01); 296 write_reg_dly((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02); 297 write_reg_dly((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03); 298 write_reg_dly((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET); 300 write_reg_dly((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01); 301 write_reg_dly((Dvt02_Vtb [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/mbx/ |
H A D | mbxfb.c | 45 #define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0) macro 272 write_reg_dly(gsctrl, GSCTRL); 277 write_reg_dly(gsadr, GSADR); 282 write_reg_dly((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) | 295 write_reg_dly((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01); 296 write_reg_dly((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02); 297 write_reg_dly((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03); 298 write_reg_dly((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET); 300 write_reg_dly((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01); 301 write_reg_dly((Dvt02_Vtb [all...] |
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