Lines Matching refs:write_reg_dly
45 #define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0)
272 write_reg_dly(gsctrl, GSCTRL);
277 write_reg_dly(gsadr, GSADR);
282 write_reg_dly((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) |
295 write_reg_dly((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01);
296 write_reg_dly((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02);
297 write_reg_dly((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03);
298 write_reg_dly((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET);
300 write_reg_dly((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01);
301 write_reg_dly((Dvt02_Vtbs(vas) | Dvt02_Vas(vas)), DVT02);
302 write_reg_dly((Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps)), DVT03);
303 write_reg_dly((Dvdet_Vdes(vas) | Dvdet_Vdef(vfps)), DVDET);
304 write_reg_dly((Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps)), DVECTRL);
306 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
308 write_reg_dly(DINTRE_VEVENT0_EN, DINTRE);
320 write_reg_dly((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL);
321 write_reg_dly((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK);
322 write_reg_dly((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK);
325 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
326 write_reg_dly((readl(PIXCLK) | PIXCLK_EN), PIXCLK);
503 write_reg_dly(vscadr, VSCADR);
504 write_reg_dly(gscadr, GSCADR);
589 write_reg_dly(vbbase, VBBASE);
590 write_reg_dly(gbbase, GBBASE);
591 write_reg_dly(vcmsk, VCMSK);
592 write_reg_dly(gdrctrl, GDRCTRL);
593 write_reg_dly(gscadr, GSCADR);
594 write_reg_dly(vscadr, VSCADR);
694 write_reg_dly((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS |
698 write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
701 write_reg_dly((Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) |
705 write_reg_dly(0xc2b, LMREFRESH);
707 write_reg_dly((LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
711 write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
721 write_reg_dly(SYSCLKSRC_PLL_2, SYSCLKSRC);
722 write_reg_dly(PIXCLKSRC_PLL_1, PIXCLKSRC);
723 write_reg_dly(0x00000000, CLKSLEEP);
730 write_reg_dly((Core_Pll_M(0xb) | Core_Pll_N(0x1) | Core_Pll_P(0x1) |
734 write_reg_dly((Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) |
738 write_reg_dly(0x00000000, VOVRCLK);
739 write_reg_dly(PIXCLK_EN, PIXCLK);
740 write_reg_dly(MEMCLK_EN, MEMCLK);
741 write_reg_dly(0x00000001, M24CLK);
742 write_reg_dly(0x00000001, MBXCLK);
743 write_reg_dly(SDCLK_EN, SDCLK);
744 write_reg_dly(0x00000001, PIXCLKDIV);
769 write_reg_dly(gsctrl, GSCTRL);
770 write_reg_dly(0x00000000, GBBASE);
771 write_reg_dly(0x00ffffff, GDRCTRL);
772 write_reg_dly((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);
773 write_reg_dly(0x00000000, GPLUT);
778 write_reg_dly(vscadr, VSCADR);
790 write_reg_dly(dsctrl, DSCTRL);
791 write_reg_dly(0xd0303010, DMCTRL);
792 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
799 write_reg_dly(SYSRST_RST, SYSRST);
802 write_reg_dly(0xffffff0c, SYSCFG);
848 write_reg_dly(LMPWR_MC_PWR_SRM, LMPWR);
853 write_reg_dly(SYSRST_RST, SYSRST);
865 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
1013 write_reg_dly(SYSRST_RST, SYSRST);