Searched refs:read_c0_ebase (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/kernel/
H A Dsmp-cmp.c99 c->core = (read_c0_ebase() >> 1) & 0xff;
H A Dcpu-probe.c744 c->core = read_c0_ebase() & 0x3ff;
H A Dsmtc.c424 cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
H A Dtraps.c1804 ebase += (read_c0_ebase() & 0x3ffff000);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/kernel/
H A Dsmp-cmp.c99 c->core = (read_c0_ebase() >> 1) & 0xff;
H A Dcpu-probe.c744 c->core = read_c0_ebase() & 0x3ff;
H A Dsmtc.c424 cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
H A Dtraps.c1804 ebase += (read_c0_ebase() & 0x3ffff000);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/cavium-octeon/
H A Dsetup.c459 uint32_t ebase = read_c0_ebase() & 0x3ffff000;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/cavium-octeon/
H A Dsetup.c459 uint32_t ebase = read_c0_ebase() & 0x3ffff000;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/
H A Dmipsregs.h1077 #define read_c0_ebase() __read_32bit_c0_register($15, 1) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/
H A Dmipsregs.h1077 #define read_c0_ebase() __read_32bit_c0_register($15, 1) macro

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