Searched refs:ramin (Results 1 - 16 of 16) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/nouveau/
H A Dnv50_instmem.c51 offset = chan->ramin->gpuobj->im_backing_start; \
146 NULL, &chan->ramin);
160 BAR0_WI32(chan->ramin->gpuobj, i, 0);
251 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
253 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
317 nouveau_gpuobj_ref_del(dev, &chan->ramin);
333 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; local
336 ramin->im_backing_suspend = vmalloc(ramin
351 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; local
[all...]
H A Dnv50_graph.c195 if (chan && chan->ramin && chan->ramin->instance == inst)
207 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; local
223 nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002);
224 nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
226 nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
227 nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0);
228 nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
229 nv_wo32(dev, ramin, (hd
[all...]
H A Dnv50_fifo.c229 uint32_t ramin_poffset = chan->ramin->gpuobj->im_pramin->start;
230 uint32_t ramin_voffset = chan->ramin->gpuobj->im_backing_start;
276 nv_wo32(dev, chan->ramin->gpuobj, 0, chan->id);
277 nv_wo32(dev, chan->ramin->gpuobj, 1,
281 nv_wo32(dev, ramfc, 0x98/4, chan->ramin->instance >> 12);
H A Dnouveau_object.c403 cpramin = chan->ramin->gpuobj;
419 cpramin = gpuobj->im_channel->ramin->gpuobj;
914 &chan->ramin);
919 pramin = chan->ramin->gpuobj;
924 nouveau_gpuobj_ref_del(dev, &chan->ramin);
961 vm_offset += chan->ramin->gpuobj->im_pramin->start;
1096 if (chan->ramin)
1097 nouveau_gpuobj_ref_del(dev, &chan->ramin);
H A Dnouveau_state.c889 dev_priv->ramin =
892 if (!dev_priv->ramin) {
899 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
901 if (!dev_priv->ramin) {
924 iounmap(dev_priv->ramin);
951 iounmap(dev_priv->ramin);
H A Dnouveau_drv.h217 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ member in struct:nouveau_channel
524 void __iomem *ramin; member in struct:drm_nouveau_private
1290 return ioread32_native(dev_priv->ramin + offset);
1296 iowrite32_native(val, dev_priv->ramin + offset);
H A Dnouveau_irq.c370 if (!chan || !chan->ramin)
373 if (inst == chan->ramin->instance)
626 if (!chan || !chan->ramin)
629 if (trap[1] == chan->ramin->instance >> 12)
H A Dnv50_display.c108 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
116 chan->ramin->gpuobj->im_pramin->start, 32768);
324 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/nouveau/
H A Dnv50_instmem.c51 offset = chan->ramin->gpuobj->im_backing_start; \
146 NULL, &chan->ramin);
160 BAR0_WI32(chan->ramin->gpuobj, i, 0);
251 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
253 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
317 nouveau_gpuobj_ref_del(dev, &chan->ramin);
333 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; local
336 ramin->im_backing_suspend = vmalloc(ramin
351 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; local
[all...]
H A Dnv50_graph.c195 if (chan && chan->ramin && chan->ramin->instance == inst)
207 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; local
223 nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002);
224 nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
226 nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
227 nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0);
228 nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
229 nv_wo32(dev, ramin, (hd
[all...]
H A Dnv50_fifo.c229 uint32_t ramin_poffset = chan->ramin->gpuobj->im_pramin->start;
230 uint32_t ramin_voffset = chan->ramin->gpuobj->im_backing_start;
276 nv_wo32(dev, chan->ramin->gpuobj, 0, chan->id);
277 nv_wo32(dev, chan->ramin->gpuobj, 1,
281 nv_wo32(dev, ramfc, 0x98/4, chan->ramin->instance >> 12);
H A Dnouveau_object.c403 cpramin = chan->ramin->gpuobj;
419 cpramin = gpuobj->im_channel->ramin->gpuobj;
914 &chan->ramin);
919 pramin = chan->ramin->gpuobj;
924 nouveau_gpuobj_ref_del(dev, &chan->ramin);
961 vm_offset += chan->ramin->gpuobj->im_pramin->start;
1096 if (chan->ramin)
1097 nouveau_gpuobj_ref_del(dev, &chan->ramin);
H A Dnouveau_state.c889 dev_priv->ramin =
892 if (!dev_priv->ramin) {
899 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
901 if (!dev_priv->ramin) {
924 iounmap(dev_priv->ramin);
951 iounmap(dev_priv->ramin);
H A Dnouveau_drv.h217 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ member in struct:nouveau_channel
524 void __iomem *ramin; member in struct:drm_nouveau_private
1290 return ioread32_native(dev_priv->ramin + offset);
1296 iowrite32_native(val, dev_priv->ramin + offset);
H A Dnouveau_irq.c370 if (!chan || !chan->ramin)
373 if (inst == chan->ramin->instance)
626 if (!chan || !chan->ramin)
629 if (trap[1] == chan->ramin->instance >> 12)
H A Dnv50_display.c108 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
116 chan->ramin->gpuobj->im_pramin->start, 32768);
324 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);

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