Searched refs:rOFDM0_XBAGCCore1 (Results 1 - 18 of 18) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/
H A Dr819xU_phy.c645 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
865 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
1718 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
1732 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1745 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
H A Dr8192U_dm.c1771 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1813 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
2188 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2251 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2258 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2451 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
H A Dr819xU_phyreg.h129 #define rOFDM0_XBAGCCore1 0xc58 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/
H A Dr819xU_phy.c645 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
865 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
1718 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
1732 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1745 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
H A Dr8192U_dm.c1771 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1813 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
2188 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2251 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2258 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2451 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
H A Dr819xU_phyreg.h129 #define rOFDM0_XBAGCCore1 0xc58 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192S_phy.c1279 priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
1375 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
3344 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3358 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3371 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3582 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
3596 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
H A Dr8192U_dm.c1798 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1840 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
2220 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2279 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2286 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2474 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
H A Dr8192S_phyreg.h210 #define rOFDM0_XBAGCCore1 0xc58 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/
H A Dr8192S_phy.c1279 priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
1375 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
3344 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3358 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3371 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3582 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
3596 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
H A Dr8192U_dm.c1798 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1840 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
2220 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2279 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2286 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2474 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
H A Dr8192S_phyreg.h210 #define rOFDM0_XBAGCCore1 0xc58 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/
H A Dr8192E_dm.c1879 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1921 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
2197 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2260 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2267 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2460 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
H A Dr819xE_phy.c2119 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2369 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
3298 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3312 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3325 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
H A Dr819xE_phyreg.h150 #define rOFDM0_XBAGCCore1 0xc58 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/
H A Dr8192E_dm.c1879 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1921 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
2197 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2260 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2267 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2460 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
H A Dr819xE_phy.c2119 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2369 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
3298 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3312 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3325 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
H A Dr819xE_phyreg.h150 #define rOFDM0_XBAGCCore1 0xc58 macro

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