1#ifndef _R819XU_PHYREG_H 2#define _R819XU_PHYREG_H 3 4 5#define RF_DATA 0x1d4 // FW will write RF data in the register. 6 7//Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 8//page 1 9#define rPMAC_Reset 0x100 10#define rPMAC_TxStart 0x104 11#define rPMAC_TxLegacySIG 0x108 12#define rPMAC_TxHTSIG1 0x10c 13#define rPMAC_TxHTSIG2 0x110 14#define rPMAC_PHYDebug 0x114 15#define rPMAC_TxPacketNum 0x118 16#define rPMAC_TxIdle 0x11c 17#define rPMAC_TxMACHeader0 0x120 18#define rPMAC_TxMACHeader1 0x124 19#define rPMAC_TxMACHeader2 0x128 20#define rPMAC_TxMACHeader3 0x12c 21#define rPMAC_TxMACHeader4 0x130 22#define rPMAC_TxMACHeader5 0x134 23#define rPMAC_TxDataType 0x138 24#define rPMAC_TxRandomSeed 0x13c 25#define rPMAC_CCKPLCPPreamble 0x140 26#define rPMAC_CCKPLCPHeader 0x144 27#define rPMAC_CCKCRC16 0x148 28#define rPMAC_OFDMRxCRC32OK 0x170 29#define rPMAC_OFDMRxCRC32Er 0x174 30#define rPMAC_OFDMRxParityEr 0x178 31#define rPMAC_OFDMRxCRC8Er 0x17c 32#define rPMAC_CCKCRxRC16Er 0x180 33#define rPMAC_CCKCRxRC32Er 0x184 34#define rPMAC_CCKCRxRC32OK 0x188 35#define rPMAC_TxStatus 0x18c 36 37//90P 38#define MCS_TXAGC 0x340 // MCS AGC 39#define CCK_TXAGC 0x348 // CCK AGC 40 41#define MacBlkCtrl 0x403 // Mac block on/off control register 42 43//page8 44#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC 45#define rFPGA0_TxInfo 0x804 46#define rFPGA0_PSDFunction 0x808 47#define rFPGA0_TxGainStage 0x80c 48#define rFPGA0_RFTiming1 0x810 49#define rFPGA0_RFTiming2 0x814 50//#define rFPGA0_XC_RFTiming 0x818 51//#define rFPGA0_XD_RFTiming 0x81c 52#define rFPGA0_XA_HSSIParameter1 0x820 53#define rFPGA0_XA_HSSIParameter2 0x824 54#define rFPGA0_XB_HSSIParameter1 0x828 55#define rFPGA0_XB_HSSIParameter2 0x82c 56#define rFPGA0_XC_HSSIParameter1 0x830 57#define rFPGA0_XC_HSSIParameter2 0x834 58#define rFPGA0_XD_HSSIParameter1 0x838 59#define rFPGA0_XD_HSSIParameter2 0x83c 60#define rFPGA0_XA_LSSIParameter 0x840 61#define rFPGA0_XB_LSSIParameter 0x844 62#define rFPGA0_XC_LSSIParameter 0x848 63#define rFPGA0_XD_LSSIParameter 0x84c 64#define rFPGA0_RFWakeUpParameter 0x850 65#define rFPGA0_RFSleepUpParameter 0x854 66#define rFPGA0_XAB_SwitchControl 0x858 67#define rFPGA0_XCD_SwitchControl 0x85c 68#define rFPGA0_XA_RFInterfaceOE 0x860 69#define rFPGA0_XB_RFInterfaceOE 0x864 70#define rFPGA0_XC_RFInterfaceOE 0x868 71#define rFPGA0_XD_RFInterfaceOE 0x86c 72#define rFPGA0_XAB_RFInterfaceSW 0x870 73#define rFPGA0_XCD_RFInterfaceSW 0x874 74#define rFPGA0_XAB_RFParameter 0x878 75#define rFPGA0_XCD_RFParameter 0x87c 76#define rFPGA0_AnalogParameter1 0x880 77#define rFPGA0_AnalogParameter2 0x884 78#define rFPGA0_AnalogParameter3 0x888 79#define rFPGA0_AnalogParameter4 0x88c 80#define rFPGA0_XA_LSSIReadBack 0x8a0 81#define rFPGA0_XB_LSSIReadBack 0x8a4 82#define rFPGA0_XC_LSSIReadBack 0x8a8 83#define rFPGA0_XD_LSSIReadBack 0x8ac 84#define rFPGA0_PSDReport 0x8b4 85#define rFPGA0_XAB_RFInterfaceRB 0x8e0 86#define rFPGA0_XCD_RFInterfaceRB 0x8e4 87 88/* Page 9 - RF mode & OFDM TxSC */ 89#define rFPGA1_RFMOD 0x900 90#define rFPGA1_TxBlock 0x904 91#define rFPGA1_DebugSelect 0x908 92#define rFPGA1_TxInfo 0x90c 93 94/* Page a */ 95#define rCCK0_System 0xa00 96#define rCCK0_AFESetting 0xa04 97#define rCCK0_CCA 0xa08 98/* AGC default value, saturation level */ 99#define rCCK0_RxAGC1 0xa0c 100/* AGC & DAGC */ 101#define rCCK0_RxAGC2 0xa10 102#define rCCK0_RxHP 0xa14 103/* Timing recovery & channel estimation threshold */ 104#define rCCK0_DSPParameter1 0xa18 105/* SQ threshold */ 106#define rCCK0_DSPParameter2 0xa1c 107#define rCCK0_TxFilter1 0xa20 108#define rCCK0_TxFilter2 0xa24 109/* Debug port and TX filter 3 */ 110#define rCCK0_DebugPort 0xa28 111#define rCCK0_FalseAlarmReport 0xa2c 112#define rCCK0_TRSSIReport 0xa50 113#define rCCK0_RxReport 0xa54 114#define rCCK0_FACounterLower 0xa5c 115#define rCCK0_FACounterUpper 0xa58 116 117/* Page c */ 118#define rOFDM0_LSTF 0xc00 119#define rOFDM0_TRxPathEnable 0xc04 120#define rOFDM0_TRMuxPar 0xc08 121#define rOFDM0_TRSWIsolation 0xc0c 122/* RxIQ DC offset, Rx digital filter, DC notch filter */ 123#define rOFDM0_XARxAFE 0xc10 124/* RxIQ imblance matrix */ 125#define rOFDM0_XARxIQImbalance 0xc14 126#define rOFDM0_XBRxAFE 0xc18 127#define rOFDM0_XBRxIQImbalance 0xc1c 128#define rOFDM0_XCRxAFE 0xc20 129#define rOFDM0_XCRxIQImbalance 0xc24 130#define rOFDM0_XDRxAFE 0xc28 131#define rOFDM0_XDRxIQImbalance 0xc2c 132/* PD, BW & SBD */ 133#define rOFDM0_RxDetector1 0xc30 134/* SBD */ 135#define rOFDM0_RxDetector2 0xc34 136/* Frame Sync */ 137#define rOFDM0_RxDetector3 0xc38 138/* PD, SBD, Frame Sync & Short-GI */ 139#define rOFDM0_RxDetector4 0xc3c 140/* Rx Sync Path */ 141#define rOFDM0_RxDSP 0xc40 142/* CFO & DAGC */ 143#define rOFDM0_CFOandDAGC 0xc44 144/* CCA Drop threshold */ 145#define rOFDM0_CCADropThreshold 0xc48 146/* Energy CCA */ 147#define rOFDM0_ECCAThreshold 0xc4c 148#define rOFDM0_XAAGCCore1 0xc50 149#define rOFDM0_XAAGCCore2 0xc54 150#define rOFDM0_XBAGCCore1 0xc58 151#define rOFDM0_XBAGCCore2 0xc5c 152#define rOFDM0_XCAGCCore1 0xc60 153#define rOFDM0_XCAGCCore2 0xc64 154#define rOFDM0_XDAGCCore1 0xc68 155#define rOFDM0_XDAGCCore2 0xc6c 156#define rOFDM0_AGCParameter1 0xc70 157#define rOFDM0_AGCParameter2 0xc74 158#define rOFDM0_AGCRSSITable 0xc78 159#define rOFDM0_HTSTFAGC 0xc7c 160#define rOFDM0_XATxIQImbalance 0xc80 161#define rOFDM0_XATxAFE 0xc84 162#define rOFDM0_XBTxIQImbalance 0xc88 163#define rOFDM0_XBTxAFE 0xc8c 164#define rOFDM0_XCTxIQImbalance 0xc90 165#define rOFDM0_XCTxAFE 0xc94 166#define rOFDM0_XDTxIQImbalance 0xc98 167#define rOFDM0_XDTxAFE 0xc9c 168#define rOFDM0_RxHPParameter 0xce0 169#define rOFDM0_TxPseudoNoiseWgt 0xce4 170#define rOFDM0_FrameSync 0xcf0 171#define rOFDM0_DFSReport 0xcf4 172#define rOFDM0_TxCoeff1 0xca4 173#define rOFDM0_TxCoeff2 0xca8 174#define rOFDM0_TxCoeff3 0xcac 175#define rOFDM0_TxCoeff4 0xcb0 176#define rOFDM0_TxCoeff5 0xcb4 177#define rOFDM0_TxCoeff6 0xcb8 178 179 180/* Page d */ 181#define rOFDM1_LSTF 0xd00 182#define rOFDM1_TRxPathEnable 0xd04 183#define rOFDM1_CFO 0xd08 184#define rOFDM1_CSI1 0xd10 185#define rOFDM1_SBD 0xd14 186#define rOFDM1_CSI2 0xd18 187#define rOFDM1_CFOTracking 0xd2c 188#define rOFDM1_TRxMesaure1 0xd34 189#define rOFDM1_IntfDet 0xd3c 190#define rOFDM1_PseudoNoiseStateAB 0xd50 191#define rOFDM1_PseudoNoiseStateCD 0xd54 192#define rOFDM1_RxPseudoNoiseWgt 0xd58 193/* cca, parity fail */ 194#define rOFDM_PHYCounter1 0xda0 195/* rate illegal, crc8 fail */ 196#define rOFDM_PHYCounter2 0xda4 197/* MCS not supported */ 198#define rOFDM_PHYCounter3 0xda8 199#define rOFDM_ShortCFOAB 0xdac 200#define rOFDM_ShortCFOCD 0xdb0 201#define rOFDM_LongCFOAB 0xdb4 202#define rOFDM_LongCFOCD 0xdb8 203#define rOFDM_TailCFOAB 0xdbc 204#define rOFDM_TailCFOCD 0xdc0 205#define rOFDM_PWMeasure1 0xdc4 206#define rOFDM_PWMeasure2 0xdc8 207#define rOFDM_BWReport 0xdcc 208#define rOFDM_AGCReport 0xdd0 209#define rOFDM_RxSNR 0xdd4 210#define rOFDM_RxEVMCSI 0xdd8 211#define rOFDM_SIGReport 0xddc 212 213/* Page e */ 214#define rTxAGC_Rate18_06 0xe00 215#define rTxAGC_Rate54_24 0xe04 216#define rTxAGC_CCK_Mcs32 0xe08 217#define rTxAGC_Mcs03_Mcs00 0xe10 218#define rTxAGC_Mcs07_Mcs04 0xe14 219#define rTxAGC_Mcs11_Mcs08 0xe18 220#define rTxAGC_Mcs15_Mcs12 0xe1c 221 222 223/* RF Zebra 1 */ 224#define rZebra1_HSSIEnable 0x0 225#define rZebra1_TRxEnable1 0x1 226#define rZebra1_TRxEnable2 0x2 227#define rZebra1_AGC 0x4 228#define rZebra1_ChargePump 0x5 229#define rZebra1_Channel 0x7 230#define rZebra1_TxGain 0x8 231#define rZebra1_TxLPF 0x9 232#define rZebra1_RxLPF 0xb 233#define rZebra1_RxHPFCorner 0xc 234 235/* Zebra 4 */ 236#define rGlobalCtrl 0 237#define rRTL8256_TxLPF 19 238#define rRTL8256_RxLPF 11 239 240/* RTL8258 */ 241#define rRTL8258_TxLPF 0x11 242#define rRTL8258_RxLPF 0x13 243#define rRTL8258_RSSILPF 0xa 244 245/* Bit Mask */ 246/* Page 1 */ 247#define bBBResetB 0x100 248#define bGlobalResetB 0x200 249#define bOFDMTxStart 0x4 250#define bCCKTxStart 0x8 251#define bCRC32Debug 0x100 252#define bPMACLoopback 0x10 253#define bTxLSIG 0xffffff 254#define bOFDMTxRate 0xf 255#define bOFDMTxReserved 0x10 256#define bOFDMTxLength 0x1ffe0 257#define bOFDMTxParity 0x20000 258#define bTxHTSIG1 0xffffff 259#define bTxHTMCSRate 0x7f 260#define bTxHTBW 0x80 261#define bTxHTLength 0xffff00 262#define bTxHTSIG2 0xffffff 263#define bTxHTSmoothing 0x1 264#define bTxHTSounding 0x2 265#define bTxHTReserved 0x4 266#define bTxHTAggreation 0x8 267#define bTxHTSTBC 0x30 268#define bTxHTAdvanceCoding 0x40 269#define bTxHTShortGI 0x80 270#define bTxHTNumberHT_LTF 0x300 271#define bTxHTCRC8 0x3fc00 272#define bCounterReset 0x10000 273#define bNumOfOFDMTx 0xffff 274#define bNumOfCCKTx 0xffff0000 275#define bTxIdleInterval 0xffff 276#define bOFDMService 0xffff0000 277#define bTxMACHeader 0xffffffff 278#define bTxDataInit 0xff 279#define bTxHTMode 0x100 280#define bTxDataType 0x30000 281#define bTxRandomSeed 0xffffffff 282#define bCCKTxPreamble 0x1 283#define bCCKTxSFD 0xffff0000 284#define bCCKTxSIG 0xff 285#define bCCKTxService 0xff00 286#define bCCKLengthExt 0x8000 287#define bCCKTxLength 0xffff0000 288#define bCCKTxCRC16 0xffff 289#define bCCKTxStatus 0x1 290#define bOFDMTxStatus 0x2 291 292/* Page 8 */ 293#define bRFMOD 0x1 294#define bJapanMode 0x2 295#define bCCKTxSC 0x30 296#define bCCKEn 0x1000000 297#define bOFDMEn 0x2000000 298#define bOFDMRxADCPhase 0x10000 299#define bOFDMTxDACPhase 0x40000 300#define bXATxAGC 0x3f 301#define bXBTxAGC 0xf00 302#define bXCTxAGC 0xf000 303#define bXDTxAGC 0xf0000 304#define bPAStart 0xf0000000 305#define bTRStart 0x00f00000 306#define bRFStart 0x0000f000 307#define bBBStart 0x000000f0 308#define bBBCCKStart 0x0000000f 309/* Reg)x814 */ 310#define bPAEnd 0xf 311#define bTREnd 0x0f000000 312#define bRFEnd 0x000f0000 313/* T2R */ 314#define bCCAMask 0x000000f0 315#define bR2RCCAMask 0x00000f00 316#define bHSSI_R2TDelay 0xf8000000 317#define bHSSI_T2RDelay 0xf80000 318/* Channel gain at continue TX. */ 319#define bContTxHSSI 0x400 320#define bIGFromCCK 0x200 321#define bAGCAddress 0x3f 322#define bRxHPTx 0x7000 323#define bRxHPT2R 0x38000 324#define bRxHPCCKIni 0xc0000 325#define bAGCTxCode 0xc00000 326#define bAGCRxCode 0x300000 327#define b3WireDataLength 0x800 328#define b3WireAddressLength 0x400 329#define b3WireRFPowerDown 0x1 330/*#define bHWSISelect 0x8 */ 331#define b5GPAPEPolarity 0x40000000 332#define b2GPAPEPolarity 0x80000000 333#define bRFSW_TxDefaultAnt 0x3 334#define bRFSW_TxOptionAnt 0x30 335#define bRFSW_RxDefaultAnt 0x300 336#define bRFSW_RxOptionAnt 0x3000 337#define bRFSI_3WireData 0x1 338#define bRFSI_3WireClock 0x2 339#define bRFSI_3WireLoad 0x4 340#define bRFSI_3WireRW 0x8 341/* 3-wire total control */ 342#define bRFSI_3Wire 0xf 343#define bRFSI_RFENV 0x10 344#define bRFSI_TRSW 0x20 345#define bRFSI_TRSWB 0x40 346#define bRFSI_ANTSW 0x100 347#define bRFSI_ANTSWB 0x200 348#define bRFSI_PAPE 0x400 349#define bRFSI_PAPE5G 0x800 350#define bBandSelect 0x1 351#define bHTSIG2_GI 0x80 352#define bHTSIG2_Smoothing 0x01 353#define bHTSIG2_Sounding 0x02 354#define bHTSIG2_Aggreaton 0x08 355#define bHTSIG2_STBC 0x30 356#define bHTSIG2_AdvCoding 0x40 357#define bHTSIG2_NumOfHTLTF 0x300 358#define bHTSIG2_CRC8 0x3fc 359#define bHTSIG1_MCS 0x7f 360#define bHTSIG1_BandWidth 0x80 361#define bHTSIG1_HTLength 0xffff 362#define bLSIG_Rate 0xf 363#define bLSIG_Reserved 0x10 364#define bLSIG_Length 0x1fffe 365#define bLSIG_Parity 0x20 366#define bCCKRxPhase 0x4 367/* LSSI "read" address */ 368#define bLSSIReadAddress 0x3f000000 369/* LSSI "read" edge signal */ 370#define bLSSIReadEdge 0x80000000 371#define bLSSIReadBackData 0xfff 372#define bLSSIReadOKFlag 0x1000 373/* 0: 44 MHz, 1: 88MHz */ 374#define bCCKSampleRate 0x8 375 376#define bRegulator0Standby 0x1 377#define bRegulatorPLLStandby 0x2 378#define bRegulator1Standby 0x4 379#define bPLLPowerUp 0x8 380#define bDPLLPowerUp 0x10 381#define bDA10PowerUp 0x20 382#define bAD7PowerUp 0x200 383#define bDA6PowerUp 0x2000 384#define bXtalPowerUp 0x4000 385#define b40MDClkPowerUP 0x8000 386#define bDA6DebugMode 0x20000 387#define bDA6Swing 0x380000 388#define bADClkPhase 0x4000000 389#define b80MClkDelay 0x18000000 390#define bAFEWatchDogEnable 0x20000000 391#define bXtalCap 0x0f000000 392#define bXtalCap01 0xc0000000 393#define bXtalCap23 0x3 394#define bXtalCap92x 0x0f000000 395#define bIntDifClkEnable 0x400 396#define bExtSigClkEnable 0x800 397#define bBandgapMbiasPowerUp 0x10000 398#define bAD11SHGain 0xc0000 399#define bAD11InputRange 0x700000 400#define bAD11OPCurrent 0x3800000 401#define bIPathLoopback 0x4000000 402#define bQPathLoopback 0x8000000 403#define bAFELoopback 0x10000000 404#define bDA10Swing 0x7e0 405#define bDA10Reverse 0x800 406#define bDAClkSource 0x1000 407#define bAD7InputRange 0x6000 408#define bAD7Gain 0x38000 409#define bAD7OutputCMMode 0x40000 410#define bAD7InputCMMode 0x380000 411#define bAD7Current 0xc00000 412#define bRegulatorAdjust 0x7000000 413#define bAD11PowerUpAtTx 0x1 414#define bDA10PSAtTx 0x10 415#define bAD11PowerUpAtRx 0x100 416#define bDA10PSAtRx 0x1000 417 418#define bCCKRxAGCFormat 0x200 419 420#define bPSDFFTSamplepPoint 0xc000 421#define bPSDAverageNum 0x3000 422#define bIQPathControl 0xc00 423#define bPSDFreq 0x3ff 424#define bPSDAntennaPath 0x30 425#define bPSDIQSwitch 0x40 426#define bPSDRxTrigger 0x400000 427#define bPSDTxTrigger 0x80000000 428#define bPSDSineToneScale 0x7f000000 429#define bPSDReport 0xffff 430 431/* Page 8 */ 432#define bOFDMTxSC 0x30000000 433#define bCCKTxOn 0x1 434#define bOFDMTxOn 0x2 435/* Reset debug page and also HWord, LWord */ 436#define bDebugPage 0xfff 437/* Reset debug page and LWord */ 438#define bDebugItem 0xff 439#define bAntL 0x10 440#define bAntNonHT 0x100 441#define bAntHT1 0x1000 442#define bAntHT2 0x10000 443#define bAntHT1S1 0x100000 444#define bAntNonHTS1 0x1000000 445 446/* Page a */ 447#define bCCKBBMode 0x3 448#define bCCKTxPowerSaving 0x80 449#define bCCKRxPowerSaving 0x40 450#define bCCKSideBand 0x10 451#define bCCKScramble 0x8 452#define bCCKAntDiversity 0x8000 453#define bCCKCarrierRecovery 0x4000 454#define bCCKTxRate 0x3000 455#define bCCKDCCancel 0x0800 456#define bCCKISICancel 0x0400 457#define bCCKMatchFilter 0x0200 458#define bCCKEqualizer 0x0100 459#define bCCKPreambleDetect 0x800000 460#define bCCKFastFalseCCA 0x400000 461#define bCCKChEstStart 0x300000 462#define bCCKCCACount 0x080000 463#define bCCKcs_lim 0x070000 464#define bCCKBistMode 0x80000000 465#define bCCKCCAMask 0x40000000 466#define bCCKTxDACPhase 0x4 467/* r_rx_clk */ 468#define bCCKRxADCPhase 0x20000000 469#define bCCKr_cp_mode0 0x0100 470#define bCCKTxDCOffset 0xf0 471#define bCCKRxDCOffset 0xf 472#define bCCKCCAMode 0xc000 473#define bCCKFalseCS_lim 0x3f00 474#define bCCKCS_ratio 0xc00000 475#define bCCKCorgBit_sel 0x300000 476#define bCCKPD_lim 0x0f0000 477#define bCCKNewCCA 0x80000000 478#define bCCKRxHPofIG 0x8000 479#define bCCKRxIG 0x7f00 480#define bCCKLNAPolarity 0x800000 481#define bCCKRx1stGain 0x7f0000 482/* CCK Rx Initial gain polarity */ 483#define bCCKRFExtend 0x20000000 484#define bCCKRxAGCSatLevel 0x1f000000 485#define bCCKRxAGCSatCount 0xe0 486/* AGCSAmp_dly */ 487#define bCCKRxRFSettle 0x1f 488#define bCCKFixedRxAGC 0x8000 489/*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ 490#define bCCKAntennaPolarity 0x2000 491#define bCCKTxFilterType 0x0c00 492#define bCCKRxAGCReportType 0x0300 493#define bCCKRxDAGCEn 0x80000000 494#define bCCKRxDAGCPeriod 0x20000000 495#define bCCKRxDAGCSatLevel 0x1f000000 496#define bCCKTimingRecovery 0x800000 497#define bCCKTxC0 0x3f0000 498#define bCCKTxC1 0x3f000000 499#define bCCKTxC2 0x3f 500#define bCCKTxC3 0x3f00 501#define bCCKTxC4 0x3f0000 502#define bCCKTxC5 0x3f000000 503#define bCCKTxC6 0x3f 504#define bCCKTxC7 0x3f00 505#define bCCKDebugPort 0xff0000 506#define bCCKDACDebug 0x0f000000 507#define bCCKFalseAlarmEnable 0x8000 508#define bCCKFalseAlarmRead 0x4000 509#define bCCKTRSSI 0x7f 510#define bCCKRxAGCReport 0xfe 511#define bCCKRxReport_AntSel 0x80000000 512#define bCCKRxReport_MFOff 0x40000000 513#define bCCKRxRxReport_SQLoss 0x20000000 514#define bCCKRxReport_Pktloss 0x10000000 515#define bCCKRxReport_Lockedbit 0x08000000 516#define bCCKRxReport_RateError 0x04000000 517#define bCCKRxReport_RxRate 0x03000000 518#define bCCKRxFACounterLower 0xff 519#define bCCKRxFACounterUpper 0xff000000 520#define bCCKRxHPAGCStart 0xe000 521#define bCCKRxHPAGCFinal 0x1c00 522 523#define bCCKRxFalseAlarmEnable 0x8000 524#define bCCKFACounterFreeze 0x4000 525 526#define bCCKTxPathSel 0x10000000 527#define bCCKDefaultRxPath 0xc000000 528#define bCCKOptionRxPath 0x3000000 529 530/* Page c */ 531#define bNumOfSTF 0x3 532#define bShift_L 0xc0 533#define bGI_TH 0xc 534#define bRxPathA 0x1 535#define bRxPathB 0x2 536#define bRxPathC 0x4 537#define bRxPathD 0x8 538#define bTxPathA 0x1 539#define bTxPathB 0x2 540#define bTxPathC 0x4 541#define bTxPathD 0x8 542#define bTRSSIFreq 0x200 543#define bADCBackoff 0x3000 544#define bDFIRBackoff 0xc000 545#define bTRSSILatchPhase 0x10000 546#define bRxIDCOffset 0xff 547#define bRxQDCOffset 0xff00 548#define bRxDFIRMode 0x1800000 549#define bRxDCNFType 0xe000000 550#define bRXIQImb_A 0x3ff 551#define bRXIQImb_B 0xfc00 552#define bRXIQImb_C 0x3f0000 553#define bRXIQImb_D 0xffc00000 554#define bDC_dc_Notch 0x60000 555#define bRxNBINotch 0x1f000000 556#define bPD_TH 0xf 557#define bPD_TH_Opt2 0xc000 558#define bPWED_TH 0x700 559#define bIfMF_Win_L 0x800 560#define bPD_Option 0x1000 561#define bMF_Win_L 0xe000 562#define bBW_Search_L 0x30000 563#define bwin_enh_L 0xc0000 564#define bBW_TH 0x700000 565#define bED_TH2 0x3800000 566#define bBW_option 0x4000000 567#define bRatio_TH 0x18000000 568#define bWindow_L 0xe0000000 569#define bSBD_Option 0x1 570#define bFrame_TH 0x1c 571#define bFS_Option 0x60 572#define bDC_Slope_check 0x80 573#define bFGuard_Counter_DC_L 0xe00 574#define bFrame_Weight_Short 0x7000 575#define bSub_Tune 0xe00000 576#define bFrame_DC_Length 0xe000000 577#define bSBD_start_offset 0x30000000 578#define bFrame_TH_2 0x7 579#define bFrame_GI2_TH 0x38 580#define bGI2_Sync_en 0x40 581#define bSarch_Short_Early 0x300 582#define bSarch_Short_Late 0xc00 583#define bSarch_GI2_Late 0x70000 584#define bCFOAntSum 0x1 585#define bCFOAcc 0x2 586#define bCFOStartOffset 0xc 587#define bCFOLookBack 0x70 588#define bCFOSumWeight 0x80 589#define bDAGCEnable 0x10000 590#define bTXIQImb_A 0x3ff 591#define bTXIQImb_B 0xfc00 592#define bTXIQImb_C 0x3f0000 593#define bTXIQImb_D 0xffc00000 594#define bTxIDCOffset 0xff 595#define bTxQDCOffset 0xff00 596#define bTxDFIRMode 0x10000 597#define bTxPesudoNoiseOn 0x4000000 598#define bTxPesudoNoise_A 0xff 599#define bTxPesudoNoise_B 0xff00 600#define bTxPesudoNoise_C 0xff0000 601#define bTxPesudoNoise_D 0xff000000 602#define bCCADropOption 0x20000 603#define bCCADropThres 0xfff00000 604#define bEDCCA_H 0xf 605#define bEDCCA_L 0xf0 606#define bLambda_ED 0x300 607#define bRxInitialGain 0x7f 608#define bRxAntDivEn 0x80 609#define bRxAGCAddressForLNA 0x7f00 610#define bRxHighPowerFlow 0x8000 611#define bRxAGCFreezeThres 0xc0000 612#define bRxFreezeStep_AGC1 0x300000 613#define bRxFreezeStep_AGC2 0xc00000 614#define bRxFreezeStep_AGC3 0x3000000 615#define bRxFreezeStep_AGC0 0xc000000 616#define bRxRssi_Cmp_En 0x10000000 617#define bRxQuickAGCEn 0x20000000 618#define bRxAGCFreezeThresMode 0x40000000 619#define bRxOverFlowCheckType 0x80000000 620#define bRxAGCShift 0x7f 621#define bTRSW_Tri_Only 0x80 622#define bPowerThres 0x300 623#define bRxAGCEn 0x1 624#define bRxAGCTogetherEn 0x2 625#define bRxAGCMin 0x4 626#define bRxHP_Ini 0x7 627#define bRxHP_TRLNA 0x70 628#define bRxHP_RSSI 0x700 629#define bRxHP_BBP1 0x7000 630#define bRxHP_BBP2 0x70000 631#define bRxHP_BBP3 0x700000 632/* The threshold for high power */ 633#define bRSSI_H 0x7f0000 634/* The threshold for ant diversity */ 635#define bRSSI_Gen 0x7f000000 636#define bRxSettle_TRSW 0x7 637#define bRxSettle_LNA 0x38 638#define bRxSettle_RSSI 0x1c0 639#define bRxSettle_BBP 0xe00 640#define bRxSettle_RxHP 0x7000 641#define bRxSettle_AntSW_RSSI 0x38000 642#define bRxSettle_AntSW 0xc0000 643#define bRxProcessTime_DAGC 0x300000 644#define bRxSettle_HSSI 0x400000 645#define bRxProcessTime_BBPPW 0x800000 646#define bRxAntennaPowerShift 0x3000000 647#define bRSSITableSelect 0xc000000 648#define bRxHP_Final 0x7000000 649#define bRxHTSettle_BBP 0x7 650#define bRxHTSettle_HSSI 0x8 651#define bRxHTSettle_RxHP 0x70 652#define bRxHTSettle_BBPPW 0x80 653#define bRxHTSettle_Idle 0x300 654#define bRxHTSettle_Reserved 0x1c00 655#define bRxHTRxHPEn 0x8000 656#define bRxHTAGCFreezeThres 0x30000 657#define bRxHTAGCTogetherEn 0x40000 658#define bRxHTAGCMin 0x80000 659#define bRxHTAGCEn 0x100000 660#define bRxHTDAGCEn 0x200000 661#define bRxHTRxHP_BBP 0x1c00000 662#define bRxHTRxHP_Final 0xe0000000 663#define bRxPWRatioTH 0x3 664#define bRxPWRatioEn 0x4 665#define bRxMFHold 0x3800 666#define bRxPD_Delay_TH1 0x38 667#define bRxPD_Delay_TH2 0x1c0 668#define bRxPD_DC_COUNT_MAX 0x600 669/*#define bRxMF_Hold 0x3800*/ 670#define bRxPD_Delay_TH 0x8000 671#define bRxProcess_Delay 0xf0000 672#define bRxSearchrange_GI2_Early 0x700000 673#define bRxFrame_Guard_Counter_L 0x3800000 674#define bRxSGI_Guard_L 0xc000000 675#define bRxSGI_Search_L 0x30000000 676#define bRxSGI_TH 0xc0000000 677#define bDFSCnt0 0xff 678#define bDFSCnt1 0xff00 679#define bDFSFlag 0xf0000 680 681#define bMFWeightSum 0x300000 682#define bMinIdxTH 0x7f000000 683 684#define bDAFormat 0x40000 685 686#define bTxChEmuEnable 0x01000000 687 688#define bTRSWIsolation_A 0x7f 689#define bTRSWIsolation_B 0x7f00 690#define bTRSWIsolation_C 0x7f0000 691#define bTRSWIsolation_D 0x7f000000 692 693#define bExtLNAGain 0x7c00 694 695/* Page d */ 696#define bSTBCEn 0x4 697#define bAntennaMapping 0x10 698#define bNss 0x20 699#define bCFOAntSumD 0x200 700#define bPHYCounterReset 0x8000000 701#define bCFOReportGet 0x4000000 702#define bOFDMContinueTx 0x10000000 703#define bOFDMSingleCarrier 0x20000000 704#define bOFDMSingleTone 0x40000000 705/*#define bRxPath1 0x01 706#define bRxPath2 0x02 707#define bRxPath3 0x04 708#define bRxPath4 0x08 709#define bTxPath1 0x10 710#define bTxPath2 0x20*/ 711#define bHTDetect 0x100 712#define bCFOEn 0x10000 713#define bCFOValue 0xfff00000 714#define bSigTone_Re 0x3f 715#define bSigTone_Im 0x7f00 716#define bCounter_CCA 0xffff 717#define bCounter_ParityFail 0xffff0000 718#define bCounter_RateIllegal 0xffff 719#define bCounter_CRC8Fail 0xffff0000 720#define bCounter_MCSNoSupport 0xffff 721#define bCounter_FastSync 0xffff 722#define bShortCFO 0xfff 723/* total */ 724#define bShortCFOTLength 12 725/* fraction */ 726#define bShortCFOFLength 11 727#define bLongCFO 0x7ff 728#define bLongCFOTLength 11 729#define bLongCFOFLength 11 730#define bTailCFO 0x1fff 731#define bTailCFOTLength 13 732#define bTailCFOFLength 12 733 734#define bmax_en_pwdB 0xffff 735#define bCC_power_dB 0xffff0000 736#define bnoise_pwdB 0xffff 737#define bPowerMeasTLength 10 738#define bPowerMeasFLength 3 739#define bRx_HT_BW 0x1 740#define bRxSC 0x6 741#define bRx_HT 0x8 742 743#define bNB_intf_det_on 0x1 744#define bIntf_win_len_cfg 0x30 745#define bNB_Intf_TH_cfg 0x1c0 746 747#define bRFGain 0x3f 748#define bTableSel 0x40 749#define bTRSW 0x80 750 751#define bRxSNR_A 0xff 752#define bRxSNR_B 0xff00 753#define bRxSNR_C 0xff0000 754#define bRxSNR_D 0xff000000 755#define bSNREVMTLength 8 756#define bSNREVMFLength 1 757 758#define bCSI1st 0xff 759#define bCSI2nd 0xff00 760#define bRxEVM1st 0xff0000 761#define bRxEVM2nd 0xff000000 762 763#define bSIGEVM 0xff 764#define bPWDB 0xff00 765#define bSGIEN 0x10000 766 767#define bSFactorQAM1 0xf 768#define bSFactorQAM2 0xf0 769#define bSFactorQAM3 0xf00 770#define bSFactorQAM4 0xf000 771#define bSFactorQAM5 0xf0000 772#define bSFactorQAM6 0xf0000 773#define bSFactorQAM7 0xf00000 774#define bSFactorQAM8 0xf000000 775#define bSFactorQAM9 0xf0000000 776#define bCSIScheme 0x100000 777 778#define bNoiseLvlTopSet 0x3 779#define bChSmooth 0x4 780#define bChSmoothCfg1 0x38 781#define bChSmoothCfg2 0x1c0 782#define bChSmoothCfg3 0xe00 783#define bChSmoothCfg4 0x7000 784#define bMRCMode 0x800000 785#define bTHEVMCfg 0x7000000 786 787#define bLoopFitType 0x1 788#define bUpdCFO 0x40 789#define bUpdCFOOffData 0x80 790#define bAdvUpdCFO 0x100 791#define bAdvTimeCtrl 0x800 792#define bUpdClko 0x1000 793#define bFC 0x6000 794#define bTrackingMode 0x8000 795#define bPhCmpEnable 0x10000 796#define bUpdClkoLTF 0x20000 797#define bComChCFO 0x40000 798#define bCSIEstiMode 0x80000 799#define bAdvUpdEqz 0x100000 800#define bUChCfg 0x7000000 801#define bUpdEqz 0x8000000 802 803/* Page e */ 804#define bTxAGCRate18_06 0x7f7f7f7f 805#define bTxAGCRate54_24 0x7f7f7f7f 806#define bTxAGCRateMCS32 0x7f 807#define bTxAGCRateCCK 0x7f00 808#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 809#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 810#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 811#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 812 813 814/* Rx Pseduo noise */ 815#define bRxPesudoNoiseOn 0x20000000 816#define bRxPesudoNoise_A 0xff 817#define bRxPesudoNoise_B 0xff00 818#define bRxPesudoNoise_C 0xff0000 819#define bRxPesudoNoise_D 0xff000000 820#define bPesudoNoiseState_A 0xffff 821#define bPesudoNoiseState_B 0xffff0000 822#define bPesudoNoiseState_C 0xffff 823#define bPesudoNoiseState_D 0xffff0000 824 825/* RF Zebra 1 */ 826#define bZebra1_HSSIEnable 0x8 827#define bZebra1_TRxControl 0xc00 828#define bZebra1_TRxGainSetting 0x07f 829#define bZebra1_RxCorner 0xc00 830#define bZebra1_TxChargePump 0x38 831#define bZebra1_RxChargePump 0x7 832#define bZebra1_ChannelNum 0xf80 833#define bZebra1_TxLPFBW 0x400 834#define bZebra1_RxLPFBW 0x600 835 836/* Zebra4 */ 837#define bRTL8256RegModeCtrl1 0x100 838#define bRTL8256RegModeCtrl0 0x40 839#define bRTL8256_TxLPFBW 0x18 840#define bRTL8256_RxLPFBW 0x600 841 842//RTL8258 843#define bRTL8258_TxLPFBW 0xc 844#define bRTL8258_RxLPFBW 0xc00 845#define bRTL8258_RSSILPFBW 0xc0 846 847/* byte endable for sb_write */ 848#define bByte0 0x1 849#define bByte1 0x2 850#define bByte2 0x4 851#define bByte3 0x8 852#define bWord0 0x3 853#define bWord1 0xc 854#define bDWord 0xf 855 856/* for PutRegsetting & GetRegSetting BitMask */ 857#define bMaskByte0 0xff 858#define bMaskByte1 0xff00 859#define bMaskByte2 0xff0000 860#define bMaskByte3 0xff000000 861#define bMaskHWord 0xffff0000 862#define bMaskLWord 0x0000ffff 863#define bMaskDWord 0xffffffff 864 865/* for PutRFRegsetting & GetRFRegSetting BitMask */ 866#define bMask12Bits 0xfff 867 868#define bEnable 0x1 869#define bDisable 0x0 870 871#define LeftAntenna 0x0 872#define RightAntenna 0x1 873 874/* 500 ms */ 875#define tCheckTxStatus 500 876/* 100 ms */ 877#define tUpdateRxCounter 100 878 879#define rateCCK 0 880#define rateOFDM 1 881#define rateHT 2 882 883/* define Register-End */ 884#define bPMAC_End 0x1ff 885#define bFPGAPHY0_End 0x8ff 886#define bFPGAPHY1_End 0x9ff 887#define bCCKPHY0_End 0xaff 888#define bOFDMPHY0_End 0xcff 889#define bOFDMPHY1_End 0xdff 890 891/*#define max debug item in each debug page 892#define bMaxItem_FPGA_PHY0 0x9 893#define bMaxItem_FPGA_PHY1 0x3 894#define bMaxItem_PHY_11B 0x16 895#define bMaxItem_OFDM_PHY0 0x29 896#define bMaxItem_OFDM_PHY1 0x0 */ 897 898#define bPMACControl 0x0 899#define bWMACControl 0x1 900#define bWNICControl 0x2 901 902#define PathA 0x0 903#define PathB 0x1 904#define PathC 0x2 905#define PathD 0x3 906 907#define rRTL8256RxMixerPole 0xb 908#define bZebraRxMixerPole 0x6 909#define rRTL8256TxBBOPBias 0x9 910#define bRTL8256TxBBOPBias 0x400 911#define rRTL8256TxBBBW 19 912#define bRTL8256TxBBBW 0x18 913 914 915#endif /* __INC_HAL8190PCIPHYREG_H */ 916