/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/ |
H A D | r819xU_phy.c | 644 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 864 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); 1717 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); 1731 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 1744 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
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H A D | r8192U_dm.c | 1770 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); 1812 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); 2187 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); 2250 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); 2257 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); 2440 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) 2450 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
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H A D | r819xU_phyreg.h | 127 #define rOFDM0_XAAGCCore1 0xc50 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/ |
H A D | r819xU_phy.c | 644 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 864 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); 1717 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); 1731 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 1744 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
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H A D | r8192U_dm.c | 1770 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); 1812 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); 2187 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); 2250 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); 2257 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); 2440 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) 2450 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
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H A D | r819xU_phyreg.h | 127 #define rOFDM0_XAAGCCore1 0xc50 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/ |
H A D | r8192S_phy.c | 1278 priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0); 1374 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 3343 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); 3357 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 3370 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); 3581 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17); 3595 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
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H A D | r8192U_dm.c | 1797 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); 1839 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); 2219 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); 2278 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); 2285 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); 2463 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) 2473 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
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H A D | r8192S_phyreg.h | 208 #define rOFDM0_XAAGCCore1 0xc50 // DIG macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/ |
H A D | r8192S_phy.c | 1278 priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0); 1374 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 3343 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); 3357 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 3370 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); 3581 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17); 3595 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
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H A D | r8192U_dm.c | 1797 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); 1839 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); 2219 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); 2278 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); 2285 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); 2463 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) 2473 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
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H A D | r8192S_phyreg.h | 208 #define rOFDM0_XAAGCCore1 0xc50 // DIG macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/ |
H A D | r8192E_dm.c | 1878 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); 1920 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); 2196 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); 2259 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); 2266 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); 2449 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) 2459 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
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H A D | r819xE_phy.c | 2118 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 2368 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); 3297 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); 3311 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 3324 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
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H A D | r819xE_phyreg.h | 148 #define rOFDM0_XAAGCCore1 0xc50 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/ |
H A D | r8192E_dm.c | 1878 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); 1920 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); 2196 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); 2259 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); 2266 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); 2449 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) 2459 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
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H A D | r819xE_phy.c | 2118 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 2368 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); 3297 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); 3311 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 3324 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
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H A D | r819xE_phyreg.h | 148 #define rOFDM0_XAAGCCore1 0xc50 macro
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