Searched refs:rFPGA0_XD_LSSIParameter (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/
H A Dr819xE_phyreg.h63 #define rFPGA0_XD_LSSIParameter 0x84c macro
H A Dr819xE_phy.c2085 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192S_phyreg.h110 #define rFPGA0_XD_LSSIParameter 0x84c macro
H A Dr8192S_phy.c1341 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h57 #define rFPGA0_XD_LSSIParameter 0x84c macro
H A Dr819xU_phy.c611 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/
H A Dr819xE_phyreg.h63 #define rFPGA0_XD_LSSIParameter 0x84c macro
H A Dr819xE_phy.c2085 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/
H A Dr8192S_phyreg.h110 #define rFPGA0_XD_LSSIParameter 0x84c macro
H A Dr8192S_phy.c1341 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h57 #define rFPGA0_XD_LSSIParameter 0x84c macro
H A Dr819xU_phy.c611 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;

Completed in 345 milliseconds