/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/ |
H A D | r8190_rtl8256.c | 454 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); // 0x880[8:5] 460 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); // 0x880[12:9] 469 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); // 0x880[8:7] 475 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11] 484 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1); // 0x880[7] 490 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1); // 0x880[11] 519 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2] 529 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] 535 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] 544 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, [all...] |
H A D | r819xE_phy.c | 2300 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue); 2306 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); 3133 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 3149 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1); 3153 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 3163 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 3185 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0); 3200 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
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H A D | r819xE_phyreg.h | 76 #define rFPGA0_AnalogParameter1 0x880 macro
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H A D | r8192E_core.c | 981 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); 987 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); 988 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/ |
H A D | r8190_rtl8256.c | 454 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); // 0x880[8:5] 460 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); // 0x880[12:9] 469 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); // 0x880[8:7] 475 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11] 484 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1); // 0x880[7] 490 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1); // 0x880[11] 519 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2] 529 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] 535 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] 544 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, [all...] |
H A D | r819xE_phy.c | 2300 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue); 2306 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); 3133 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 3149 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1); 3153 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 3163 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 3185 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0); 3200 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
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H A D | r819xE_phyreg.h | 76 #define rFPGA0_AnalogParameter1 0x880 macro
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H A D | r8192E_core.c | 981 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); 987 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); 988 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/ |
H A D | r819xU_phy.c | 817 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue); 1087 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] 1093 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] 1108 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] 1114 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] 1558 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 1589 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
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H A D | r819xU_phyreg.h | 70 #define rFPGA0_AnalogParameter1 0x880 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/ |
H A D | r819xU_phy.c | 817 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue); 1087 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] 1093 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] 1108 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] 1114 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] 1558 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 1589 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
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H A D | r819xU_phyreg.h | 70 #define rFPGA0_AnalogParameter1 0x880 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/ |
H A D | r8192S_phyreg.h | 129 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? macro 525 #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/ |
H A D | r8192S_phyreg.h | 129 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? macro 525 #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
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