Searched refs:rCCK0_System (Results 1 - 12 of 12) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/ |
| H A D | r8192S_phy.c | 2164 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3155 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3258 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
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| H A D | r8192S_phyreg.h | 158 #define rCCK0_System 0xa00 macro
587 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/ |
| H A D | r8192S_phy.c | 2164 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3155 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3258 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
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| H A D | r8192S_phyreg.h | 158 #define rCCK0_System 0xa00 macro
587 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/ |
| H A D | r819xE_phyreg.h | 95 #define rCCK0_System 0xa00 macro
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| H A D | r819xE_phy.c | 3162 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3180 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/ |
| H A D | r819xU_phyreg.h | 89 #define rCCK0_System 0xa00 macro
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| H A D | r819xU_phy.c | 1588 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/ |
| H A D | r819xE_phyreg.h | 95 #define rCCK0_System 0xa00 macro
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| H A D | r819xE_phy.c | 3162 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3180 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/ |
| H A D | r819xU_phyreg.h | 89 #define rCCK0_System 0xa00 macro
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| H A D | r819xU_phy.c | 1588 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
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