Searched refs:qla4_8xxx_reg (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/qla4xxx/
H A Dql4_isr.c464 ? readl(&ha->qla4_8xxx_reg->mailbox_out[i])
475 ? readl(&ha->qla4_8xxx_reg->mailbox_out[i])
655 readl(&ha->qla4_8xxx_reg->mailbox_out[0]));
658 writel(0, &ha->qla4_8xxx_reg->host_int);
659 readl(&ha->qla4_8xxx_reg->host_int);
702 writel(0, &ha->qla4_8xxx_reg->host_int);
843 if (!(readl(&ha->qla4_8xxx_reg->host_int) &
848 intr_status = readl(&ha->qla4_8xxx_reg->host_status);
909 if (!(readl(&ha->qla4_8xxx_reg->host_int) &
915 intr_status = readl(&ha->qla4_8xxx_reg
[all...]
H A Dql4_mbx.c85 intr_status = readl(&ha->qla4_8xxx_reg->host_int);
91 intr_status = readl(&ha->qla4_8xxx_reg->host_status);
122 writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
123 writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
124 readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
125 writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
180 readl(&ha->qla4_8xxx_reg->host_int);
184 readl(&ha->qla4_8xxx_reg->host_status);
H A Dql4_iocb.c230 writel(ha->response_out, &ha->qla4_8xxx_reg->rsp_q_out);
231 readl(&ha->qla4_8xxx_reg->rsp_q_out);
H A Dql4_init.c133 (unsigned long __iomem *)&ha->qla4_8xxx_reg->req_q_out);
135 (unsigned long __iomem *)&ha->qla4_8xxx_reg->rsp_q_in);
137 (unsigned long __iomem *)&ha->qla4_8xxx_reg->rsp_q_out);
H A Dql4_def.h575 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */ member in struct:scsi_qla_host
H A Dql4_os.c1461 ha->qla4_8xxx_reg =
1598 return (uint16_t)le32_to_cpu(readl(&ha->qla4_8xxx_reg->req_q_out));
1608 return (uint16_t)le32_to_cpu(readl(&ha->qla4_8xxx_reg->rsp_q_in));
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/qla4xxx/
H A Dql4_isr.c464 ? readl(&ha->qla4_8xxx_reg->mailbox_out[i])
475 ? readl(&ha->qla4_8xxx_reg->mailbox_out[i])
655 readl(&ha->qla4_8xxx_reg->mailbox_out[0]));
658 writel(0, &ha->qla4_8xxx_reg->host_int);
659 readl(&ha->qla4_8xxx_reg->host_int);
702 writel(0, &ha->qla4_8xxx_reg->host_int);
843 if (!(readl(&ha->qla4_8xxx_reg->host_int) &
848 intr_status = readl(&ha->qla4_8xxx_reg->host_status);
909 if (!(readl(&ha->qla4_8xxx_reg->host_int) &
915 intr_status = readl(&ha->qla4_8xxx_reg
[all...]
H A Dql4_mbx.c85 intr_status = readl(&ha->qla4_8xxx_reg->host_int);
91 intr_status = readl(&ha->qla4_8xxx_reg->host_status);
122 writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
123 writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
124 readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
125 writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
180 readl(&ha->qla4_8xxx_reg->host_int);
184 readl(&ha->qla4_8xxx_reg->host_status);
H A Dql4_iocb.c230 writel(ha->response_out, &ha->qla4_8xxx_reg->rsp_q_out);
231 readl(&ha->qla4_8xxx_reg->rsp_q_out);
H A Dql4_init.c133 (unsigned long __iomem *)&ha->qla4_8xxx_reg->req_q_out);
135 (unsigned long __iomem *)&ha->qla4_8xxx_reg->rsp_q_in);
137 (unsigned long __iomem *)&ha->qla4_8xxx_reg->rsp_q_out);
H A Dql4_def.h575 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */ member in struct:scsi_qla_host
H A Dql4_os.c1461 ha->qla4_8xxx_reg =
1598 return (uint16_t)le32_to_cpu(readl(&ha->qla4_8xxx_reg->req_q_out));
1608 return (uint16_t)le32_to_cpu(readl(&ha->qla4_8xxx_reg->rsp_q_in));

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