1/* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2006 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8#ifndef __QL4_DEF_H 9#define __QL4_DEF_H 10 11#include <linux/kernel.h> 12#include <linux/init.h> 13#include <linux/types.h> 14#include <linux/module.h> 15#include <linux/list.h> 16#include <linux/pci.h> 17#include <linux/dma-mapping.h> 18#include <linux/sched.h> 19#include <linux/slab.h> 20#include <linux/dmapool.h> 21#include <linux/mempool.h> 22#include <linux/spinlock.h> 23#include <linux/workqueue.h> 24#include <linux/delay.h> 25#include <linux/interrupt.h> 26#include <linux/mutex.h> 27 28#include <net/tcp.h> 29#include <scsi/scsi.h> 30#include <scsi/scsi_host.h> 31#include <scsi/scsi_device.h> 32#include <scsi/scsi_cmnd.h> 33#include <scsi/scsi_transport.h> 34#include <scsi/scsi_transport_iscsi.h> 35 36#include "ql4_dbg.h" 37#include "ql4_nx.h" 38 39#if defined(CONFIG_PCIEAER) 40#include <linux/aer.h> 41#else 42/* AER releated */ 43static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) 44{ 45 return -EINVAL; 46} 47static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev) 48{ 49 return -EINVAL; 50} 51static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) 52{ 53 return -EINVAL; 54} 55#endif 56 57#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 58#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 59#endif 60 61#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 62#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 63#endif 64 65#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 66#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 67#endif 68 69#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022 70#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022 71#endif 72 73#define QLA_SUCCESS 0 74#define QLA_ERROR 1 75 76/* 77 * Data bit definitions 78 */ 79#define BIT_0 0x1 80#define BIT_1 0x2 81#define BIT_2 0x4 82#define BIT_3 0x8 83#define BIT_4 0x10 84#define BIT_5 0x20 85#define BIT_6 0x40 86#define BIT_7 0x80 87#define BIT_8 0x100 88#define BIT_9 0x200 89#define BIT_10 0x400 90#define BIT_11 0x800 91#define BIT_12 0x1000 92#define BIT_13 0x2000 93#define BIT_14 0x4000 94#define BIT_15 0x8000 95#define BIT_16 0x10000 96#define BIT_17 0x20000 97#define BIT_18 0x40000 98#define BIT_19 0x80000 99#define BIT_20 0x100000 100#define BIT_21 0x200000 101#define BIT_22 0x400000 102#define BIT_23 0x800000 103#define BIT_24 0x1000000 104#define BIT_25 0x2000000 105#define BIT_26 0x4000000 106#define BIT_27 0x8000000 107#define BIT_28 0x10000000 108#define BIT_29 0x20000000 109#define BIT_30 0x40000000 110#define BIT_31 0x80000000 111 112/** 113 * Macros to help code, maintain, etc. 114 **/ 115#define ql4_printk(level, ha, format, arg...) \ 116 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 117 118 119/* 120 * Host adapter default definitions 121 ***********************************/ 122#define MAX_HBAS 16 123#define MAX_BUSES 1 124#define MAX_TARGETS MAX_DEV_DB_ENTRIES 125#define MAX_LUNS 0xffff 126#define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */ 127#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES 128#define MAX_PDU_ENTRIES 32 129#define INVALID_ENTRY 0xFFFF 130#define MAX_CMDS_TO_RISC 1024 131#define MAX_SRBS MAX_CMDS_TO_RISC 132#define MBOX_AEN_REG_COUNT 5 133#define MAX_INIT_RETRIES 5 134 135/* 136 * Buffer sizes 137 */ 138#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 139#define RESPONSE_QUEUE_DEPTH 64 140#define QUEUE_SIZE 64 141#define DMA_BUFFER_SIZE 512 142 143/* 144 * Misc 145 */ 146#define MAC_ADDR_LEN 6 /* in bytes */ 147#define IP_ADDR_LEN 4 /* in bytes */ 148#define IPv6_ADDR_LEN 16 /* IPv6 address size */ 149#define DRIVER_NAME "qla4xxx" 150 151#define MAX_LINKED_CMDS_PER_LUN 3 152#define MAX_REQS_SERVICED_PER_INTR 1 153 154#define ISCSI_IPADDR_SIZE 4 /* IP address size */ 155#define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 156#define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 157 158#define QL4_SESS_RECOVERY_TMO 30 /* iSCSI session */ 159 /* recovery timeout */ 160 161#define LSDW(x) ((u32)((u64)(x))) 162#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 163 164/* 165 * Retry & Timeout Values 166 */ 167#define MBOX_TOV 60 168#define SOFT_RESET_TOV 30 169#define RESET_INTR_TOV 3 170#define SEMAPHORE_TOV 10 171#define ADAPTER_INIT_TOV 30 172#define ADAPTER_RESET_TOV 180 173#define EXTEND_CMD_TOV 60 174#define WAIT_CMD_TOV 30 175#define EH_WAIT_CMD_TOV 120 176#define FIRMWARE_UP_TOV 60 177#define RESET_FIRMWARE_TOV 30 178#define LOGOUT_TOV 10 179#define IOCB_TOV_MARGIN 10 180#define RELOGIN_TOV 18 181#define ISNS_DEREG_TOV 5 182 183#define MAX_RESET_HA_RETRIES 2 184 185#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 186 187/* 188 * SCSI Request Block structure (srb) that is placed 189 * on cmd->SCp location of every I/O [We have 22 bytes available] 190 */ 191struct srb { 192 struct list_head list; /* (8) */ 193 struct scsi_qla_host *ha; /* HA the SP is queued on */ 194 struct ddb_entry *ddb; 195 uint16_t flags; /* (1) Status flags. */ 196 197#define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 198#define SRB_GOT_SENSE BIT_4 /* sense data recieved. */ 199 uint8_t state; /* (1) Status flags. */ 200 201#define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 202#define SRB_FREE_STATE 1 203#define SRB_ACTIVE_STATE 3 204#define SRB_ACTIVE_TIMEOUT_STATE 4 205#define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 206 207 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 208 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 209 struct kref srb_ref; /* reference count for this srb */ 210 uint32_t fw_ddb_index; 211 uint8_t err_id; /* error id */ 212#define SRB_ERR_PORT 1 /* Request failed because "port down" */ 213#define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 214#define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 215#define SRB_ERR_OTHER 4 216 217 uint16_t reserved; 218 uint16_t iocb_tov; 219 uint16_t iocb_cnt; /* Number of used iocbs */ 220 uint16_t cc_stat; 221 222 /* Used for extended sense / status continuation */ 223 uint8_t *req_sense_ptr; 224 uint16_t req_sense_len; 225 uint16_t reserved2; 226}; 227 228/* 229 * Asynchronous Event Queue structure 230 */ 231struct aen { 232 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 233}; 234 235struct ql4_aen_log { 236 int count; 237 struct aen entry[MAX_AEN_ENTRIES]; 238}; 239 240/* 241 * Device Database (DDB) structure 242 */ 243struct ddb_entry { 244 struct list_head list; /* ddb list */ 245 struct scsi_qla_host *ha; 246 struct iscsi_cls_session *sess; 247 struct iscsi_cls_conn *conn; 248 249 atomic_t state; /* DDB State */ 250 251 unsigned long flags; /* DDB Flags */ 252 253 unsigned long dev_scan_wait_to_start_relogin; 254 unsigned long dev_scan_wait_to_complete_relogin; 255 256 uint16_t fw_ddb_index; /* DDB firmware index */ 257 uint16_t options; 258 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 259 260 uint32_t CmdSn; 261 uint16_t target_session_id; 262 uint16_t connection_id; 263 uint16_t exe_throttle; /* Max mumber of cmds outstanding 264 * simultaneously */ 265 uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to 266 * complete */ 267 uint16_t default_relogin_timeout; /* Max time to wait for 268 * relogin to complete */ 269 uint16_t tcp_source_port_num; 270 uint32_t default_time2wait; /* Default Min time between 271 * relogins (+aens) */ 272 273 atomic_t retry_relogin_timer; /* Min Time between relogins 274 * (4000 only) */ 275 atomic_t relogin_timer; /* Max Time to wait for relogin to complete */ 276 atomic_t relogin_retry_count; /* Num of times relogin has been 277 * retried */ 278 279 uint16_t port; 280 uint32_t tpgt; 281 uint8_t ip_addr[IP_ADDR_LEN]; 282 uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */ 283 uint8_t iscsi_alias[0x20]; 284 uint8_t isid[6]; 285 uint16_t iscsi_max_burst_len; 286 uint16_t iscsi_max_outsnd_r2t; 287 uint16_t iscsi_first_burst_len; 288 uint16_t iscsi_max_rcv_data_seg_len; 289 uint16_t iscsi_max_snd_data_seg_len; 290 291 struct in6_addr remote_ipv6_addr; 292 struct in6_addr link_local_ipv6_addr; 293}; 294 295/* 296 * DDB states. 297 */ 298#define DDB_STATE_DEAD 0 /* We can no longer talk to 299 * this device */ 300#define DDB_STATE_ONLINE 1 /* Device ready to accept 301 * commands */ 302#define DDB_STATE_MISSING 2 /* Device logged off, trying 303 * to re-login */ 304 305/* 306 * DDB flags. 307 */ 308#define DF_RELOGIN 0 /* Relogin to device */ 309#define DF_NO_RELOGIN 1 /* Do not relogin if IOCTL 310 * logged it out */ 311#define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 312#define DF_FO_MASKED 3 313 314 315#include "ql4_fw.h" 316#include "ql4_nvram.h" 317 318struct ql82xx_hw_data { 319 /* Offsets for flash/nvram access (set to ~0 if not used). */ 320 uint32_t flash_conf_off; 321 uint32_t flash_data_off; 322 323 uint32_t fdt_wrt_disable; 324 uint32_t fdt_erase_cmd; 325 uint32_t fdt_block_size; 326 uint32_t fdt_unprotect_sec_cmd; 327 uint32_t fdt_protect_sec_cmd; 328 329 uint32_t flt_region_flt; 330 uint32_t flt_region_fdt; 331 uint32_t flt_region_boot; 332 uint32_t flt_region_bootload; 333 uint32_t flt_region_fw; 334 uint32_t reserved; 335}; 336 337struct qla4_8xxx_legacy_intr_set { 338 uint32_t int_vec_bit; 339 uint32_t tgt_status_reg; 340 uint32_t tgt_mask_reg; 341 uint32_t pci_int_reg; 342}; 343 344/* MSI-X Support */ 345 346#define QLA_MSIX_DEFAULT 0x00 347#define QLA_MSIX_RSP_Q 0x01 348 349#define QLA_MSIX_ENTRIES 2 350#define QLA_MIDX_DEFAULT 0 351#define QLA_MIDX_RSP_Q 1 352 353struct ql4_msix_entry { 354 int have_irq; 355 uint16_t msix_vector; 356 uint16_t msix_entry; 357}; 358 359/* 360 * ISP Operations 361 */ 362struct isp_operations { 363 int (*iospace_config) (struct scsi_qla_host *ha); 364 void (*pci_config) (struct scsi_qla_host *); 365 void (*disable_intrs) (struct scsi_qla_host *); 366 void (*enable_intrs) (struct scsi_qla_host *); 367 int (*start_firmware) (struct scsi_qla_host *); 368 irqreturn_t (*intr_handler) (int , void *); 369 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 370 int (*reset_chip) (struct scsi_qla_host *); 371 int (*reset_firmware) (struct scsi_qla_host *); 372 void (*queue_iocb) (struct scsi_qla_host *); 373 void (*complete_iocb) (struct scsi_qla_host *); 374 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 375 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 376 int (*get_sys_info) (struct scsi_qla_host *); 377}; 378 379/* 380 * Linux Host Adapter structure 381 */ 382struct scsi_qla_host { 383 /* Linux adapter configuration data */ 384 unsigned long flags; 385 386#define AF_ONLINE 0 /* 0x00000001 */ 387#define AF_INIT_DONE 1 /* 0x00000002 */ 388#define AF_MBOX_COMMAND 2 /* 0x00000004 */ 389#define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 390#define AF_DPC_SCHEDULED 5 /* 0x00000020 */ 391#define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 392#define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 393#define AF_LINK_UP 8 /* 0x00000100 */ 394#define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 395#define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 396#define AF_HBA_GOING_AWAY 12 /* 0x00001000 */ 397#define AF_INTx_ENABLED 15 /* 0x00008000 */ 398#define AF_MSI_ENABLED 16 /* 0x00010000 */ 399#define AF_MSIX_ENABLED 17 /* 0x00020000 */ 400#define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */ 401#define AF_FW_RECOVERY 19 /* 0x00080000 */ 402#define AF_EEH_BUSY 20 /* 0x00100000 */ 403#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ 404 405 unsigned long dpc_flags; 406 407#define DPC_RESET_HA 1 /* 0x00000002 */ 408#define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 409#define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 410#define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */ 411#define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 412#define DPC_ISNS_RESTART 7 /* 0x00000080 */ 413#define DPC_AEN 9 /* 0x00000200 */ 414#define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 415#define DPC_LINK_CHANGED 18 /* 0x00040000 */ 416#define DPC_RESET_ACTIVE 20 /* 0x00040000 */ 417#define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/ 418#define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/ 419 420 421 struct Scsi_Host *host; /* pointer to host data */ 422 uint32_t tot_ddbs; 423 424 uint16_t iocb_cnt; 425 426 /* SRB cache. */ 427#define SRB_MIN_REQ 128 428 mempool_t *srb_mempool; 429 430 /* pci information */ 431 struct pci_dev *pdev; 432 433 struct isp_reg __iomem *reg; /* Base I/O address */ 434 unsigned long pio_address; 435 unsigned long pio_length; 436#define MIN_IOBASE_LEN 0x100 437 438 uint16_t req_q_count; 439 440 unsigned long host_no; 441 442 /* NVRAM registers */ 443 struct eeprom_data *nvram; 444 spinlock_t hardware_lock ____cacheline_aligned; 445 uint32_t eeprom_cmd_data; 446 447 /* Counters for general statistics */ 448 uint64_t isr_count; 449 uint64_t adapter_error_count; 450 uint64_t device_error_count; 451 uint64_t total_io_count; 452 uint64_t total_mbytes_xferred; 453 uint64_t link_failure_count; 454 uint64_t invalid_crc_count; 455 uint32_t bytes_xfered; 456 uint32_t spurious_int_count; 457 uint32_t aborted_io_count; 458 uint32_t io_timeout_count; 459 uint32_t mailbox_timeout_count; 460 uint32_t seconds_since_last_intr; 461 uint32_t seconds_since_last_heartbeat; 462 uint32_t mac_index; 463 464 /* Info Needed for Management App */ 465 /* --- From GetFwVersion --- */ 466 uint32_t firmware_version[2]; 467 uint32_t patch_number; 468 uint32_t build_number; 469 uint32_t board_id; 470 471 /* --- From Init_FW --- */ 472 /* init_cb_t *init_cb; */ 473 uint16_t firmware_options; 474 uint16_t tcp_options; 475 uint8_t ip_address[IP_ADDR_LEN]; 476 uint8_t subnet_mask[IP_ADDR_LEN]; 477 uint8_t gateway[IP_ADDR_LEN]; 478 uint8_t alias[32]; 479 uint8_t name_string[256]; 480 uint8_t heartbeat_interval; 481 482 /* --- From FlashSysInfo --- */ 483 uint8_t my_mac[MAC_ADDR_LEN]; 484 uint8_t serial_number[16]; 485 486 /* --- From GetFwState --- */ 487 uint32_t firmware_state; 488 uint32_t addl_fw_state; 489 490 /* Linux kernel thread */ 491 struct workqueue_struct *dpc_thread; 492 struct work_struct dpc_work; 493 494 /* Linux timer thread */ 495 struct timer_list timer; 496 uint32_t timer_active; 497 498 /* Recovery Timers */ 499 uint32_t discovery_wait; 500 atomic_t check_relogin_timeouts; 501 uint32_t retry_reset_ha_cnt; 502 uint32_t isp_reset_timer; /* reset test timer */ 503 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 504 int eh_start; 505 struct list_head free_srb_q; 506 uint16_t free_srb_q_count; 507 uint16_t num_srbs_allocated; 508 509 /* DMA Memory Block */ 510 void *queues; 511 dma_addr_t queues_dma; 512 unsigned long queues_len; 513 514#define MEM_ALIGN_VALUE \ 515 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 516 sizeof(struct queue_entry)) 517 /* request and response queue variables */ 518 dma_addr_t request_dma; 519 struct queue_entry *request_ring; 520 struct queue_entry *request_ptr; 521 dma_addr_t response_dma; 522 struct queue_entry *response_ring; 523 struct queue_entry *response_ptr; 524 dma_addr_t shadow_regs_dma; 525 struct shadow_regs *shadow_regs; 526 uint16_t request_in; /* Current indexes. */ 527 uint16_t request_out; 528 uint16_t response_in; 529 uint16_t response_out; 530 531 /* aen queue variables */ 532 uint16_t aen_q_count; /* Number of available aen_q entries */ 533 uint16_t aen_in; /* Current indexes */ 534 uint16_t aen_out; 535 struct aen aen_q[MAX_AEN_ENTRIES]; 536 537 struct ql4_aen_log aen_log;/* tracks all aens */ 538 539 /* This mutex protects several threads to do mailbox commands 540 * concurrently. 541 */ 542 struct mutex mbox_sem; 543 544 /* temporary mailbox status registers */ 545 volatile uint8_t mbox_status_count; 546 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 547 548 /* local device database list (contains internal ddb entries) */ 549 struct list_head ddb_list; 550 551 /* Map ddb_list entry by FW ddb index */ 552 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 553 554 /* Saved srb for status continuation entry processing */ 555 struct srb *status_srb; 556 557 /* IPv6 support info from InitFW */ 558 uint8_t acb_version; 559 uint8_t ipv4_addr_state; 560 uint16_t ipv4_options; 561 562 uint32_t resvd2; 563 uint32_t ipv6_options; 564 uint32_t ipv6_addl_options; 565 uint8_t ipv6_link_local_state; 566 uint8_t ipv6_addr0_state; 567 uint8_t ipv6_addr1_state; 568 uint8_t ipv6_default_router_state; 569 struct in6_addr ipv6_link_local_addr; 570 struct in6_addr ipv6_addr0; 571 struct in6_addr ipv6_addr1; 572 struct in6_addr ipv6_default_router_addr; 573 574 /* qla82xx specific fields */ 575 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */ 576 unsigned long nx_pcibase; /* Base I/O address */ 577 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ 578 unsigned long nx_db_wr_ptr; /* Door bell write pointer */ 579 unsigned long first_page_group_start; 580 unsigned long first_page_group_end; 581 582 uint32_t crb_win; 583 uint32_t curr_window; 584 uint32_t ddr_mn_window; 585 unsigned long mn_win_crb; 586 unsigned long ms_win_crb; 587 int qdr_sn_window; 588 rwlock_t hw_lock; 589 uint16_t func_num; 590 int link_width; 591 592 struct qla4_8xxx_legacy_intr_set nx_legacy_intr; 593 u32 nx_crb_mask; 594 595 uint8_t revision_id; 596 uint32_t fw_heartbeat_counter; 597 598 struct isp_operations *isp_ops; 599 struct ql82xx_hw_data hw; 600 601 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES]; 602 603 uint32_t nx_dev_init_timeout; 604 uint32_t nx_reset_timeout; 605 606 struct completion mbx_intr_comp; 607}; 608 609static inline int is_ipv4_enabled(struct scsi_qla_host *ha) 610{ 611 return ((ha->ipv4_options & IPOPT_IPv4_PROTOCOL_ENABLE) != 0); 612} 613 614static inline int is_ipv6_enabled(struct scsi_qla_host *ha) 615{ 616 return ((ha->ipv6_options & IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0); 617} 618 619static inline int is_qla4010(struct scsi_qla_host *ha) 620{ 621 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 622} 623 624static inline int is_qla4022(struct scsi_qla_host *ha) 625{ 626 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 627} 628 629static inline int is_qla4032(struct scsi_qla_host *ha) 630{ 631 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 632} 633 634static inline int is_qla8022(struct scsi_qla_host *ha) 635{ 636 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 637} 638 639/* Note: Currently AER/EEH is now supported only for 8022 cards 640 * This function needs to be updated when AER/EEH is enabled 641 * for other cards. 642 */ 643static inline int is_aer_supported(struct scsi_qla_host *ha) 644{ 645 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 646} 647 648static inline int adapter_up(struct scsi_qla_host *ha) 649{ 650 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 651 (test_bit(AF_LINK_UP, &ha->flags) != 0); 652} 653 654static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 655{ 656 return (struct scsi_qla_host *)shost->hostdata; 657} 658 659static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 660{ 661 return (is_qla4010(ha) ? 662 &ha->reg->u1.isp4010.nvram : 663 &ha->reg->u1.isp4022.semaphore); 664} 665 666static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 667{ 668 return (is_qla4010(ha) ? 669 &ha->reg->u1.isp4010.nvram : 670 &ha->reg->u1.isp4022.nvram); 671} 672 673static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 674{ 675 return (is_qla4010(ha) ? 676 &ha->reg->u2.isp4010.ext_hw_conf : 677 &ha->reg->u2.isp4022.p0.ext_hw_conf); 678} 679 680static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 681{ 682 return (is_qla4010(ha) ? 683 &ha->reg->u2.isp4010.port_status : 684 &ha->reg->u2.isp4022.p0.port_status); 685} 686 687static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 688{ 689 return (is_qla4010(ha) ? 690 &ha->reg->u2.isp4010.port_ctrl : 691 &ha->reg->u2.isp4022.p0.port_ctrl); 692} 693 694static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 695{ 696 return (is_qla4010(ha) ? 697 &ha->reg->u2.isp4010.port_err_status : 698 &ha->reg->u2.isp4022.p0.port_err_status); 699} 700 701static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 702{ 703 return (is_qla4010(ha) ? 704 &ha->reg->u2.isp4010.gp_out : 705 &ha->reg->u2.isp4022.p0.gp_out); 706} 707 708static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 709{ 710 return (is_qla4010(ha) ? 711 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 712 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 713} 714 715int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 716void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 717int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 718 719static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 720{ 721 if (is_qla4010(a)) 722 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 723 QL4010_FLASH_SEM_BITS); 724 else 725 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 726 (QL4022_RESOURCE_BITS_BASE_CODE | 727 (a->mac_index)) << 13); 728} 729 730static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 731{ 732 if (is_qla4010(a)) 733 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 734 else 735 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 736} 737 738static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 739{ 740 if (is_qla4010(a)) 741 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 742 QL4010_NVRAM_SEM_BITS); 743 else 744 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 745 (QL4022_RESOURCE_BITS_BASE_CODE | 746 (a->mac_index)) << 10); 747} 748 749static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 750{ 751 if (is_qla4010(a)) 752 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 753 else 754 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 755} 756 757static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 758{ 759 if (is_qla4010(a)) 760 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 761 QL4010_DRVR_SEM_BITS); 762 else 763 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 764 (QL4022_RESOURCE_BITS_BASE_CODE | 765 (a->mac_index)) << 1); 766} 767 768static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 769{ 770 if (is_qla4010(a)) 771 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 772 else 773 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 774} 775 776/*---------------------------------------------------------------------------*/ 777 778/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 779#define PRESERVE_DDB_LIST 0 780#define REBUILD_DDB_LIST 1 781 782/* Defines for process_aen() */ 783#define PROCESS_ALL_AENS 0 784#define FLUSH_DDB_CHANGED_AENS 1 785#define RELOGIN_DDB_CHANGED_AENS 2 786 787#endif /*_QLA4XXX_H */ 788