Searched refs:pTmrHw (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-bcmring/csp/tmr/
H A DtmrHw.c96 pTmrHw[timerId].LoadValue = 0;
97 pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
98 pTmrHw[timerId].Control = 0;
99 pTmrHw[timerId].BackgroundLoad = 0;
101 pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
103 if (pTmrHw[timerId].RawInterruptStatus) {
104 pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
125 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
128 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
131 pTmrHw[timerI
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-bcmring/csp/tmr/
H A DtmrHw.c96 pTmrHw[timerId].LoadValue = 0;
97 pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
98 pTmrHw[timerId].Control = 0;
99 pTmrHw[timerId].BackgroundLoad = 0;
101 pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
103 if (pTmrHw[timerId].RawInterruptStatus) {
104 pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
125 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
128 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
131 pTmrHw[timerI
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-bcmring/include/mach/csp/
H A DtmrHw_reg.h80 #define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-bcmring/include/mach/csp/
H A DtmrHw_reg.h80 #define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR) macro

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