Searched refs:bXtalCap (Results 1 - 8 of 8) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/
H A Dr819xE_phyreg.h391 #define bXtalCap 0x0f000000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192S_phyreg.h533 #define bXtalCap 0x0f000000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h361 #define bXtalCap 0x0f000000 macro
H A Dr819xU_phy.c817 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/
H A Dr819xE_phyreg.h391 #define bXtalCap 0x0f000000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/
H A Dr8192S_phyreg.h533 #define bXtalCap 0x0f000000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h361 #define bXtalCap 0x0f000000 macro
H A Dr819xU_phy.c817 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue);

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