Searched refs:bXCTxAGC (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/
H A Dr819xE_phyreg.h302 #define bXCTxAGC 0xf000 macro
H A Dr819xE_phy.c2294 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
2435 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192S_phyreg.h441 #define bXCTxAGC 0xf000 macro
H A Dr8192S_phy.c1798 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h279 #define bXCTxAGC 0xf000 macro
H A Dr819xU_phy.c813 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/
H A Dr819xE_phyreg.h302 #define bXCTxAGC 0xf000 macro
H A Dr819xE_phy.c2294 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
2435 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/
H A Dr8192S_phyreg.h441 #define bXCTxAGC 0xf000 macro
H A Dr8192S_phy.c1798 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h279 #define bXCTxAGC 0xf000 macro
H A Dr819xU_phy.c813 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue);

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