Searched refs:bMaskByte1 (Results 1 - 24 of 24) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192S_phy.h85 #define bMaskByte1 0xff00 macro
H A Dr8192U_dm.c1796 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1811 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1838 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2137 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2177 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2216 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2321 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
H A Dr8192S_phy.c3342 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3368 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3386 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
H A Dr8192S_phyreg.h980 #define bMaskByte1 0xff00 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/
H A Dr819xU_phy.h53 #define bMaskByte1 0xff00 macro
H A Dr819xU_phy.c1716 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
1742 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
1768 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
H A Dr8192U_dm.c1769 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1784 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1811 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2105 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2145 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2184 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2293 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
H A Dr819xU_phyreg.h817 #define bMaskByte1 0xff00 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/
H A Dr8192S_phy.h85 #define bMaskByte1 0xff00 macro
H A Dr8192U_dm.c1796 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1811 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1838 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2137 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2177 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2216 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2321 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
H A Dr8192S_phy.c3342 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3368 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3386 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
H A Dr8192S_phyreg.h980 #define bMaskByte1 0xff00 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/
H A Dr819xU_phy.h53 #define bMaskByte1 0xff00 macro
H A Dr819xU_phy.c1716 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
1742 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
1768 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
H A Dr8192U_dm.c1769 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1784 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1811 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2105 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2145 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2184 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2293 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
H A Dr819xU_phyreg.h817 #define bMaskByte1 0xff00 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/
H A Dr819xE_phy.h98 #define bMaskByte1 0xff00 macro
H A Dr8192E_dm.c1877 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1892 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1919 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2114 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2154 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2193 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2302 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
H A Dr819xE_phyreg.h858 #define bMaskByte1 0xff00 macro
H A Dr819xE_phy.c3296 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3322 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3341 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/
H A Dr819xE_phy.h98 #define bMaskByte1 0xff00 macro
H A Dr8192E_dm.c1877 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1892 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1919 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2114 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2154 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2193 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2302 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
H A Dr819xE_phyreg.h858 #define bMaskByte1 0xff00 macro
H A Dr819xE_phy.c3296 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3322 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3341 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON

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