| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-shmobile/ |
| H A D | intc-sh7367.c | 299 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2, enumerator in enum:__anon11884
341 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
391 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
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| H A D | intc-sh7372.c | 378 _2DDMAC, enumerator in enum:__anon11886
422 INTCS_VECT(_2DDMAC, 0xa00),
485 { 0, 0, 0, _2DDMAC,
527 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
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| H A D | intc-sh7377.c | 368 _2DDMAC,
431 INTCS_VECT(_2DDMAC, 0x0A00),
517 { 0, 0, 0, _2DDMAC,
565 { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-shmobile/ |
| H A D | intc-sh7367.c | 299 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2, enumerator in enum:__anon23577
341 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
391 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
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| H A D | intc-sh7372.c | 378 _2DDMAC, enumerator in enum:__anon23579
422 INTCS_VECT(_2DDMAC, 0xa00),
485 { 0, 0, 0, _2DDMAC,
527 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
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| H A D | intc-sh7377.c | 368 _2DDMAC,
431 INTCS_VECT(_2DDMAC, 0x0A00),
517 { 0, 0, 0, _2DDMAC,
565 { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/ |
| H A D | setup-sh7724.c | 950 _2DDMAC, enumerator in enum:__anon25814
1051 INTC_VECT(_2DDMAC, 0x4A0),
1114 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1135 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/kernel/cpu/sh4a/ |
| H A D | setup-sh7724.c | 950 _2DDMAC, enumerator in enum:__anon14121
1051 INTC_VECT(_2DDMAC, 0x4A0),
1114 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1135 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
|