1/* 2 * sh7367 processor support - INTC hardware block 3 * 4 * Copyright (C) 2010 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19#include <linux/kernel.h> 20#include <linux/init.h> 21#include <linux/interrupt.h> 22#include <linux/irq.h> 23#include <linux/io.h> 24#include <linux/sh_intc.h> 25#include <asm/mach-types.h> 26#include <asm/mach/arch.h> 27 28enum { 29 UNUSED_INTCA = 0, 30 ENABLED, 31 DISABLED, 32 33 /* interrupt sources INTCA */ 34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, 35 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, 36 DIRC, 37 CRYPT1_ERR, CRYPT2_STD, 38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, 39 ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX, 40 ETM11_ACQCMP, ETM11_FULL, 41 MFI_MFIM, MFI_MFIS, 42 BBIF1, BBIF2, 43 USBDMAC_USHDMI, 44 USBHS_USHI0, USBHS_USHI1, 45 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, 46 KEYSC_KEY, 47 SCIFA0, SCIFA1, SCIFA2, SCIFA3, 48 MSIOF2, MSIOF1, 49 SCIFA4, SCIFA5, SCIFB, 50 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 51 SDHI0, 52 SDHI1, 53 MSU_MSU, MSU_MSU2, 54 IREM, 55 SIU, 56 SPU, 57 IRDA, 58 TPU0, TPU1, TPU2, TPU3, TPU4, 59 LCRC, 60 PINT1, PINT2, 61 TTI20, 62 MISTY, 63 DDM, 64 SDHI2, 65 RWDT0, RWDT1, 66 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, 67 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, 68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, 69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, 70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, 71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, 72 73 /* interrupt groups INTCA */ 74 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, 75 ETM11, ARM11, USBHS, FLCTL, IIC1 76}; 77 78static struct intc_vect intca_vectors[] __initdata = { 79 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), 80 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), 81 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), 82 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), 83 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), 84 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), 85 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), 86 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), 87 INTC_VECT(DIRC, 0x0560), 88 INTC_VECT(CRYPT1_ERR, 0x05e0), 89 INTC_VECT(CRYPT2_STD, 0x0700), 90 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), 91 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), 92 INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840), 93 INTC_VECT(ARM11_COMMRX, 0x0860), 94 INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0), 95 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), 96 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), 97 INTC_VECT(USBDMAC_USHDMI, 0x0a00), 98 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), 99 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), 100 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), 101 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), 102 INTC_VECT(KEYSC_KEY, 0x0be0), 103 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), 104 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), 105 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), 106 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), 107 INTC_VECT(SCIFB, 0x0d60), 108 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), 109 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), 110 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20), 111 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60), 112 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0), 113 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0), 114 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), 115 INTC_VECT(IREM, 0x0f60), 116 INTC_VECT(SIU, 0x0fa0), 117 INTC_VECT(SPU, 0x0fc0), 118 INTC_VECT(IRDA, 0x0480), 119 INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0), 120 INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500), 121 INTC_VECT(TPU4, 0x0520), 122 INTC_VECT(LCRC, 0x0540), 123 INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020), 124 INTC_VECT(TTI20, 0x1100), 125 INTC_VECT(MISTY, 0x1120), 126 INTC_VECT(DDM, 0x1140), 127 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220), 128 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260), 129 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), 130 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), 131 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), 132 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), 133 INTC_VECT(DMAC_2_DADERR, 0x20c0), 134 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), 135 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), 136 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), 137 INTC_VECT(DMAC2_2_DADERR, 0x21c0), 138 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), 139 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), 140 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), 141 INTC_VECT(DMAC3_2_DADERR, 0x22c0), 142}; 143 144static struct intc_group intca_groups[] __initdata = { 145 INTC_GROUP(DMAC_1, DMAC_1_DEI0, 146 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), 147 INTC_GROUP(DMAC_2, DMAC_2_DEI4, 148 DMAC_2_DEI5, DMAC_2_DADERR), 149 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, 150 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), 151 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, 152 DMAC2_2_DEI5, DMAC2_2_DADERR), 153 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, 154 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), 155 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, 156 DMAC3_2_DEI5, DMAC3_2_DADERR), 157 INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL), 158 INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX), 159 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), 160 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, 161 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 162 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 163}; 164 165static struct intc_mask_reg intca_mask_registers[] __initdata = { 166 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ 167 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 168 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ 169 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 170 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ 171 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, 172 ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } }, 173 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ 174 { CRYPT1_ERR, CRYPT2_STD, DIRC, 0, 175 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, 176 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ 177 { PINT1, PINT2, 0, 0, 178 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, 179 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ 180 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, 181 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, 182 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ 183 { DDM, 0, 0, 0, 184 0, 0, ETM11_FULL, ETM11_ACQCMP } }, 185 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ 186 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, 187 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, 188 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ 189 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 190 0, 0, MSIOF2, 0 } }, 191 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 192 { DISABLED, DISABLED, ENABLED, ENABLED, 193 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 194 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 195 { DISABLED, DISABLED, ENABLED, ENABLED, 196 TTI20, USBDMAC_USHDMI, SPU, SIU } }, 197 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 198 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 199 CMT2, USBHS_USHI1, USBHS_USHI0, 0 } }, 200 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ 201 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, 202 0, 0, 0, 0 } }, 203 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ 204 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, 205 LCRC, MSU_MSU2, IREM, MSU_MSU } }, 206 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ 207 { 0, 0, TPU0, TPU1, 208 TPU2, TPU3, TPU4, 0 } }, 209 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ 210 { DISABLED, DISABLED, ENABLED, ENABLED, 211 MISTY, CMT3, RWDT1, RWDT0 } }, 212}; 213 214static struct intc_prio_reg intca_prio_registers[] __initdata = { 215 { 0xe6900010, 0, 32, 4, /* INTPRI00A */ 216 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 217 { 0xe6900014, 0, 32, 4, /* INTPRI10A */ 218 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 219 220 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, 221 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } }, 222 { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD, 223 CMT1_CMT11, ARM11 } }, 224 { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2, 225 CMT1_CMT12, TPU4 } }, 226 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, 227 MFI_MFIM, USBHS } }, 228 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, 229 0, CMT1_CMT10 } }, 230 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, 231 SCIFA2, SCIFA3 } }, 232 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI, 233 FLCTL, SDHI0 } }, 234 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, 235 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } }, 236 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } }, 237 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, 238 { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, 239 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } }, 240 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, 241}; 242 243static struct intc_sense_reg intca_sense_registers[] __initdata = { 244 { 0xe6900000, 16, 2, /* ICR1A */ 245 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 246 { 0xe6900004, 16, 2, /* ICR2A */ 247 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 248}; 249 250static struct intc_mask_reg intca_ack_registers[] __initdata = { 251 { 0xe6900020, 0, 8, /* INTREQ00A */ 252 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 253 { 0xe6900024, 0, 8, /* INTREQ10A */ 254 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 255}; 256 257static struct intc_desc intca_desc __initdata = { 258 .name = "sh7367-intca", 259 .force_enable = ENABLED, 260 .force_disable = DISABLED, 261 .hw = INTC_HW_DESC(intca_vectors, intca_groups, 262 intca_mask_registers, intca_prio_registers, 263 intca_sense_registers, intca_ack_registers), 264}; 265 266enum { 267 UNUSED_INTCS = 0, 268 269 INTCS, 270 271 /* interrupt sources INTCS */ 272 VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3, 273 VIO3_VOU, 274 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3, 275 VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2, 276 VPU, 277 SGX530, 278 _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3, 279 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, 280 IPMMU_IPMMUB, IPMMU_IPMMUS, 281 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR, 282 MSIOF, 283 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, 284 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, 285 CMT, 286 TSIF, 287 IPMMUI, 288 MVI3, 289 ICB, 290 PEP, 291 ASA, 292 BEM, 293 VE2HO, 294 HQE, 295 JPEG, 296 LCDC, 297 298 /* interrupt groups INTCS */ 299 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2, 300}; 301 302static struct intc_vect intcs_vectors[] = { 303 INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720), 304 INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760), 305 INTCS_VECT(VIO3_VOU, 0x780), 306 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820), 307 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860), 308 INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0), 309 INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0), 310 INTCS_VECT(VPU, 0x980), 311 INTCS_VECT(SGX530, 0x9e0), 312 INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20), 313 INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60), 314 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), 315 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), 316 INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60), 317 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0), 318 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0), 319 INTCS_VECT(MSIOF, 0xd20), 320 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20), 321 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60), 322 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0), 323 INTCS_VECT(TMU_TUNI2, 0xec0), 324 INTCS_VECT(CMT, 0xf00), 325 INTCS_VECT(TSIF, 0xf20), 326 INTCS_VECT(IPMMUI, 0xf60), 327 INTCS_VECT(MVI3, 0x420), 328 INTCS_VECT(ICB, 0x480), 329 INTCS_VECT(PEP, 0x4a0), 330 INTCS_VECT(ASA, 0x4c0), 331 INTCS_VECT(BEM, 0x4e0), 332 INTCS_VECT(VE2HO, 0x520), 333 INTCS_VECT(HQE, 0x540), 334 INTCS_VECT(JPEG, 0x560), 335 INTCS_VECT(LCDC, 0x580), 336 337 INTC_VECT(INTCS, 0xf80), 338}; 339 340static struct intc_group intcs_groups[] __initdata = { 341 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1, 342 _2DDMAC_2DDM2, _2DDMAC_2DDM3), 343 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1, 344 RTDMAC_1_DEI2, RTDMAC_1_DEI3), 345 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR), 346 INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3), 347 INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2), 348 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), 349 INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB), 350 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), 351}; 352 353static struct intc_mask_reg intcs_mask_registers[] = { 354 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ 355 { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU, 356 VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } }, 357 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ 358 { VIO3_VOU, 0, VE2HO, VPU, 359 0, 0, 0, 0 } }, 360 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ 361 { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0, 362 BEM, ASA, PEP, ICB } }, 363 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ 364 { 0, 0, MVI3, 0, 365 JPEG, HQE, 0, LCDC } }, 366 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ 367 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4, 368 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, 369 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ 370 { 0, 0, MSIOF, 0, 371 SGX530, 0, 0, 0 } }, 372 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ 373 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, 374 0, 0, 0, 0 } }, 375 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ 376 { 0, 0, 0, CMT, 377 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, 378 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */ 379 { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0, 380 0, 0, 0, 0 } }, 381 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ 382 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, 383 0, 0, IPMMUI, TSIF } }, 384 { 0xffd20104, 0, 16, /* INTAMASK */ 385 { 0, 0, 0, 0, 0, 0, 0, 0, 386 0, 0, 0, 0, 0, 0, 0, INTCS } }, 387}; 388 389/* Priority is needed for INTCA to receive the INTCS interrupt */ 390static struct intc_prio_reg intcs_prio_registers[] = { 391 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } }, 392 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } }, 393 { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, 394 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } }, 395 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } }, 396 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1, 397 TMU_TUNI2, 0 } }, 398 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } }, 399 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } }, 400 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } }, 401 { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } }, 402 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } }, 403 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, 404}; 405 406static struct resource intcs_resources[] __initdata = { 407 [0] = { 408 .start = 0xffd20000, 409 .end = 0xffd2ffff, 410 .flags = IORESOURCE_MEM, 411 } 412}; 413 414static struct intc_desc intcs_desc __initdata = { 415 .name = "sh7367-intcs", 416 .resource = intcs_resources, 417 .num_resources = ARRAY_SIZE(intcs_resources), 418 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, 419 intcs_prio_registers, NULL, NULL), 420}; 421 422static void intcs_demux(unsigned int irq, struct irq_desc *desc) 423{ 424 void __iomem *reg = (void *)get_irq_data(irq); 425 unsigned int evtcodeas = ioread32(reg); 426 427 generic_handle_irq(intcs_evt2irq(evtcodeas)); 428} 429 430void __init sh7367_init_irq(void) 431{ 432 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 433 434 register_intc_controller(&intca_desc); 435 register_intc_controller(&intcs_desc); 436 437 /* demux using INTEVTSA */ 438 set_irq_data(evt2irq(0xf80), (void *)intevtsa); 439 set_irq_chained_handler(evt2irq(0xf80), intcs_demux); 440} 441