Searched refs:WITH_TARGET_WORD_BITSIZE (Results 1 - 25 of 75) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/common/
H A Dsim-bits.c62 #if (WITH_TARGET_WORD_BITSIZE == 64)
65 #if (WITH_TARGET_WORD_BITSIZE == 32)
76 #if (WITH_TARGET_WORD_BITSIZE == 16)
97 #if (WITH_TARGET_WORD_BITSIZE == 64)
100 #if (WITH_TARGET_WORD_BITSIZE == 32)
111 #if (WITH_TARGET_WORD_BITSIZE == 16)
132 #if (WITH_TARGET_WORD_BITSIZE == 64)
135 #if (WITH_TARGET_WORD_BITSIZE == 32)
147 #if (WITH_TARGET_WORD_BITSIZE == 16)
168 #if (WITH_TARGET_WORD_BITSIZE
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H A Dsim-alu.h546 #define ALU_BEGIN XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_BEGIN)
547 #define ALU_SET XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_SET)
548 #define ALU_SET_CARRY XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_SET_CARRY)
550 #define ALU_HAD_OVERFLOW XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_HAD_OVERFLOW)
551 #define ALU_HAD_CARRY XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_HAD_CARRY)
553 #define ALU_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_RESULT)
554 #define ALU_OVERFLOW_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_OVERFLOW_RESULT)
555 #define ALU_CARRY_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_CARRY_RESULT)
585 #define ALU_ADD XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_ADD)
623 #define ALU_ADDC XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_ADD
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H A Dsim-core.h298 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
299 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
300 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
337 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
338 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
339 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
H A Dsim-types.h158 #if (WITH_TARGET_WORD_BITSIZE == 64)
162 #if (WITH_TARGET_WORD_BITSIZE == 32)
166 #if (WITH_TARGET_WORD_BITSIZE == 16)
H A Dsim-config.h298 #ifndef WITH_TARGET_WORD_BITSIZE macro
299 #define WITH_TARGET_WORD_BITSIZE 32
303 #define WITH_TARGET_ADDRESS_BITSIZE WITH_TARGET_WORD_BITSIZE
307 #define WITH_TARGET_CELL_BITSIZE WITH_TARGET_WORD_BITSIZE
322 MSB as 31, 63. Define this to be (WITH_TARGET_WORD_BITSIZE - 1) */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/common/
H A Dsim-bits.c62 #if (WITH_TARGET_WORD_BITSIZE == 64)
65 #if (WITH_TARGET_WORD_BITSIZE == 32)
76 #if (WITH_TARGET_WORD_BITSIZE == 16)
97 #if (WITH_TARGET_WORD_BITSIZE == 64)
100 #if (WITH_TARGET_WORD_BITSIZE == 32)
111 #if (WITH_TARGET_WORD_BITSIZE == 16)
132 #if (WITH_TARGET_WORD_BITSIZE == 64)
135 #if (WITH_TARGET_WORD_BITSIZE == 32)
147 #if (WITH_TARGET_WORD_BITSIZE == 16)
168 #if (WITH_TARGET_WORD_BITSIZE
[all...]
H A Dsim-alu.h546 #define ALU_BEGIN XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_BEGIN)
547 #define ALU_SET XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_SET)
548 #define ALU_SET_CARRY XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_SET_CARRY)
550 #define ALU_HAD_OVERFLOW XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_HAD_OVERFLOW)
551 #define ALU_HAD_CARRY XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_HAD_CARRY)
553 #define ALU_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_RESULT)
554 #define ALU_OVERFLOW_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_OVERFLOW_RESULT)
555 #define ALU_CARRY_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_CARRY_RESULT)
585 #define ALU_ADD XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_ADD)
623 #define ALU_ADDC XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_ADD
[all...]
H A Dsim-core.h298 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
299 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
300 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
337 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
338 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
339 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
H A Dsim-types.h158 #if (WITH_TARGET_WORD_BITSIZE == 64)
162 #if (WITH_TARGET_WORD_BITSIZE == 32)
166 #if (WITH_TARGET_WORD_BITSIZE == 16)
H A Dsim-config.h298 #ifndef WITH_TARGET_WORD_BITSIZE macro
299 #define WITH_TARGET_WORD_BITSIZE 32
303 #define WITH_TARGET_ADDRESS_BITSIZE WITH_TARGET_WORD_BITSIZE
307 #define WITH_TARGET_CELL_BITSIZE WITH_TARGET_WORD_BITSIZE
322 MSB as 31, 63. Define this to be (WITH_TARGET_WORD_BITSIZE - 1) */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/common/
H A Dsim-bits.c62 #if (WITH_TARGET_WORD_BITSIZE == 64)
65 #if (WITH_TARGET_WORD_BITSIZE == 32)
76 #if (WITH_TARGET_WORD_BITSIZE == 16)
97 #if (WITH_TARGET_WORD_BITSIZE == 64)
100 #if (WITH_TARGET_WORD_BITSIZE == 32)
111 #if (WITH_TARGET_WORD_BITSIZE == 16)
132 #if (WITH_TARGET_WORD_BITSIZE == 64)
135 #if (WITH_TARGET_WORD_BITSIZE == 32)
147 #if (WITH_TARGET_WORD_BITSIZE == 16)
168 #if (WITH_TARGET_WORD_BITSIZE
[all...]
H A Dsim-alu.h546 #define ALU_BEGIN XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_BEGIN)
547 #define ALU_SET XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_SET)
548 #define ALU_SET_CARRY XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_SET_CARRY)
550 #define ALU_HAD_OVERFLOW XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_HAD_OVERFLOW)
551 #define ALU_HAD_CARRY XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_HAD_CARRY)
553 #define ALU_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_RESULT)
554 #define ALU_OVERFLOW_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_OVERFLOW_RESULT)
555 #define ALU_CARRY_RESULT XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_CARRY_RESULT)
585 #define ALU_ADD XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_ADD)
623 #define ALU_ADDC XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_ADD
[all...]
H A Dsim-core.h298 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
299 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
300 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
337 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
338 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
339 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
H A Dsim-types.h158 #if (WITH_TARGET_WORD_BITSIZE == 64)
162 #if (WITH_TARGET_WORD_BITSIZE == 32)
166 #if (WITH_TARGET_WORD_BITSIZE == 16)
H A Dsim-config.h298 #ifndef WITH_TARGET_WORD_BITSIZE macro
299 #define WITH_TARGET_WORD_BITSIZE 32
303 #define WITH_TARGET_ADDRESS_BITSIZE WITH_TARGET_WORD_BITSIZE
307 #define WITH_TARGET_CELL_BITSIZE WITH_TARGET_WORD_BITSIZE
322 MSB as 31, 63. Define this to be (WITH_TARGET_WORD_BITSIZE - 1) */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/ppc/
H A Didecode_expression.h106 #define _ALU_RESULT_VAL(CA,OE,Rc) (WITH_TARGET_WORD_BITSIZE == 64 \
116 #if (WITH_TARGET_WORD_BITSIZE == 64)
124 #if (WITH_TARGET_WORD_BITSIZE == 32)
133 #if (WITH_TARGET_WORD_BITSIZE == 64)
148 #if (WITH_TARGET_WORD_BITSIZE == 32)
158 #if (WITH_TARGET_WORD_BITSIZE == 64)
165 #if (WITH_TARGET_WORD_BITSIZE == 32)
175 #if (WITH_TARGET_WORD_BITSIZE == 64)
177 #if (WITH_TARGET_WORD_BITSIZE == 32)
187 #if (WITH_TARGET_WORD_BITSIZE
[all...]
H A Dbits.c84 #if (WITH_TARGET_WORD_BITSIZE == 64)
103 #if (WITH_TARGET_WORD_BITSIZE == 64)
H A Dwords.h101 #if (WITH_TARGET_WORD_BITSIZE == 64)
H A Dvm.c132 #if (WITH_TARGET_WORD_BITSIZE == 64)
146 #if (WITH_TARGET_WORD_BITSIZE == 64)
167 #if (WITH_TARGET_WORD_BITSIZE == 64)
171 #if (WITH_TARGET_WORD_BITSIZE == 32)
207 #if (WITH_TARGET_WORD_BITSIZE == 64)
304 #if (WITH_TARGET_WORD_BITSIZE == 32)
308 #if (WITH_TARGET_WORD_BITSIZE == 64)
324 #if (WITH_TARGET_WORD_BITSIZE == 32)
327 #if (WITH_TARGET_WORD_BITSIZE == 64)
336 #if (WITH_TARGET_WORD_BITSIZE
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/ppc/
H A Didecode_expression.h106 #define _ALU_RESULT_VAL(CA,OE,Rc) (WITH_TARGET_WORD_BITSIZE == 64 \
116 #if (WITH_TARGET_WORD_BITSIZE == 64)
124 #if (WITH_TARGET_WORD_BITSIZE == 32)
133 #if (WITH_TARGET_WORD_BITSIZE == 64)
148 #if (WITH_TARGET_WORD_BITSIZE == 32)
158 #if (WITH_TARGET_WORD_BITSIZE == 64)
165 #if (WITH_TARGET_WORD_BITSIZE == 32)
175 #if (WITH_TARGET_WORD_BITSIZE == 64)
177 #if (WITH_TARGET_WORD_BITSIZE == 32)
187 #if (WITH_TARGET_WORD_BITSIZE
[all...]
H A Dbits.c84 #if (WITH_TARGET_WORD_BITSIZE == 64)
103 #if (WITH_TARGET_WORD_BITSIZE == 64)
H A Dwords.h101 #if (WITH_TARGET_WORD_BITSIZE == 64)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/ppc/
H A Didecode_expression.h106 #define _ALU_RESULT_VAL(CA,OE,Rc) (WITH_TARGET_WORD_BITSIZE == 64 \
116 #if (WITH_TARGET_WORD_BITSIZE == 64)
124 #if (WITH_TARGET_WORD_BITSIZE == 32)
133 #if (WITH_TARGET_WORD_BITSIZE == 64)
148 #if (WITH_TARGET_WORD_BITSIZE == 32)
158 #if (WITH_TARGET_WORD_BITSIZE == 64)
165 #if (WITH_TARGET_WORD_BITSIZE == 32)
175 #if (WITH_TARGET_WORD_BITSIZE == 64)
177 #if (WITH_TARGET_WORD_BITSIZE == 32)
187 #if (WITH_TARGET_WORD_BITSIZE
[all...]
H A Dbits.c84 #if (WITH_TARGET_WORD_BITSIZE == 64)
103 #if (WITH_TARGET_WORD_BITSIZE == 64)
H A Dwords.h101 #if (WITH_TARGET_WORD_BITSIZE == 64)

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