Searched refs:TIMER_ENABLE (Results 1 - 25 of 30) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-msm/
H A Dtimer.c35 #define TIMER_ENABLE 0x0008 macro
101 writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
105 writel(0, clock->regbase + TIMER_ENABLE);
177 writel(0, clock->regbase + TIMER_ENABLE);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-msm/
H A Dtimer.c35 #define TIMER_ENABLE 0x0008 macro
101 writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
105 writel(0, clock->regbase + TIMER_ENABLE);
177 writel(0, clock->regbase + TIMER_ENABLE);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/include/asm/
H A Dgptimers.h22 # define TIMER0_GROUP_REG TIMER_ENABLE
52 # define TIMER0_GROUP_REG TIMER_ENABLE
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/include/asm/
H A Dgptimers.h22 # define TIMER0_GROUP_REG TIMER_ENABLE
52 # define TIMER0_GROUP_REG TIMER_ENABLE
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/watchdog/
H A Dixp2000_wdt.c48 ixp2000_reg_write(IXP2000_T4_CTL, TIMER_DIVIDER_256 | TIMER_ENABLE);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/watchdog/
H A Dixp2000_wdt.c48 ixp2000_reg_write(IXP2000_T4_CTL, TIMER_DIVIDER_256 | TIMER_ENABLE);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-ixp2000/include/mach/
H A Dixp2000-regs.h139 #define TIMER_ENABLE 0x00000080 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-ixp2000/include/mach/
H A Dixp2000-regs.h139 #define TIMER_ENABLE 0x00000080 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h527 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
528 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
H A DdefBF532.h97 #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ macro
569 /* TIMER_ENABLE Register */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h527 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
528 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
H A DdefBF532.h97 #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ macro
569 /* TIMER_ENABLE Register */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/kernel/
H A Dbfin_gpio.c37 AWA_inen = TIMER_ENABLE,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/kernel/
H A Dbfin_gpio.c37 AWA_inen = TIMER_ENABLE,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h207 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
208 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
H A DdefBF51x_base.h137 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
754 /* TIMER_ENABLE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h224 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
225 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
H A DdefBF52x_base.h132 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
755 /* TIMER_ENABLE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h207 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
208 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
H A DdefBF51x_base.h137 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
754 /* TIMER_ENABLE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h224 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
225 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
H A DdefBF52x_base.h132 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
755 /* TIMER_ENABLE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h115 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
1119 /* TIMER_ENABLE Masks */
H A DcdefBF534.h190 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
191 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h115 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
1119 /* TIMER_ENABLE Masks */

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