Searched refs:TIMER_CTRL (Results 1 - 20 of 20) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/include/asm/hardware/
H A Darm_timer.h15 #define TIMER_CTRL 0x08 /* ACVR rw */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/include/asm/hardware/
H A Darm_timer.h15 #define TIMER_CTRL 0x08 /* ACVR rw */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-orion/
H A Dtime.c34 #define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) macro
145 u = readl(TIMER_CTRL);
147 writel(u, TIMER_CTRL);
177 u = readl(TIMER_CTRL);
178 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
183 u = readl(TIMER_CTRL);
184 writel(u & ~TIMER1_EN, TIMER_CTRL);
246 u = readl(TIMER_CTRL);
247 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-orion/
H A Dtime.c34 #define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) macro
145 u = readl(TIMER_CTRL);
147 writel(u, TIMER_CTRL);
177 u = readl(TIMER_CTRL);
178 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
183 u = readl(TIMER_CTRL);
184 writel(u & ~TIMER1_EN, TIMER_CTRL);
246 u = readl(TIMER_CTRL);
247 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-versatile/
H A Dtimer-sp.c60 writel(0, clksrc_base + TIMER_CTRL);
64 clksrc_base + TIMER_CTRL);
93 writel(ctrl, clkevt_base + TIMER_CTRL);
112 writel(ctrl, clkevt_base + TIMER_CTRL);
118 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
121 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-versatile/
H A Dtimer-sp.c60 writel(0, clksrc_base + TIMER_CTRL);
64 clksrc_base + TIMER_CTRL);
93 writel(ctrl, clkevt_base + TIMER_CTRL);
112 writel(ctrl, clkevt_base + TIMER_CTRL);
118 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
121 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-bcmring/
H A Dcore.c239 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
245 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
248 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
312 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
316 TIMER1_VA_BASE + TIMER_CTRL);
324 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
328 TIMER3_VA_BASE + TIMER_CTRL);
347 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
348 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
349 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-bcmring/
H A Dcore.c239 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
245 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
248 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
312 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
316 TIMER1_VA_BASE + TIMER_CTRL);
324 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
328 TIMER3_VA_BASE + TIMER_CTRL);
347 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
348 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
349 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-integrator/
H A Dintegrator_ap.c383 writel(ctrl, base + TIMER_CTRL);
409 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
414 writel(ctrl, clkevt_base + TIMER_CTRL);
419 writel(ctrl, clkevt_base + TIMER_CTRL);
424 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
426 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
428 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
464 writel(ctrl, clkevt_base + TIMER_CTRL);
482 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
483 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
[all...]
H A Dintegrator_cp.c588 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
589 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
590 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-integrator/
H A Dintegrator_ap.c383 writel(ctrl, base + TIMER_CTRL);
409 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
414 writel(ctrl, clkevt_base + TIMER_CTRL);
419 writel(ctrl, clkevt_base + TIMER_CTRL);
424 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
426 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
428 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
464 writel(ctrl, clkevt_base + TIMER_CTRL);
482 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
483 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
[all...]
H A Dintegrator_cp.c588 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
589 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
590 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/watchdog/
H A Dorion_wdt.c31 #define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) macro
71 reg = readl(TIMER_CTRL);
73 writel(reg, TIMER_CTRL);
95 reg = readl(TIMER_CTRL);
97 writel(reg, TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/watchdog/
H A Dorion_wdt.c31 #define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) macro
71 reg = readl(TIMER_CTRL);
73 writel(reg, TIMER_CTRL);
95 reg = readl(TIMER_CTRL);
97 writel(reg, TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-realview/
H A Dcore.c688 writel(0, timer0_va_base + TIMER_CTRL);
689 writel(0, timer1_va_base + TIMER_CTRL);
690 writel(0, timer2_va_base + TIMER_CTRL);
691 writel(0, timer3_va_base + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-realview/
H A Dcore.c688 writel(0, timer0_va_base + TIMER_CTRL);
689 writel(0, timer1_va_base + TIMER_CTRL);
690 writel(0, timer2_va_base + TIMER_CTRL);
691 writel(0, timer3_va_base + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-versatile/
H A Dcore.c887 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
888 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
889 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
890 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-versatile/
H A Dcore.c887 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
888 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
889 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
890 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-vexpress/
H A Dv2m.c53 writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
54 writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-vexpress/
H A Dv2m.c53 writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
54 writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);

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