1/* 2 * derived from linux/arch/arm/mach-versatile/core.c 3 * linux/arch/arm/mach-bcmring/core.c 4 * 5 * Copyright (C) 1999 - 2003 ARM Limited 6 * Copyright (C) 2000 Deep Blue Solutions Ltd 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22/* Portions copyright Broadcom 2008 */ 23 24#include <linux/init.h> 25#include <linux/device.h> 26#include <linux/dma-mapping.h> 27#include <linux/platform_device.h> 28#include <linux/sysdev.h> 29#include <linux/interrupt.h> 30#include <linux/amba/bus.h> 31#include <linux/clocksource.h> 32#include <linux/clockchips.h> 33 34#include <mach/csp/mm_addr.h> 35#include <mach/hardware.h> 36#include <asm/clkdev.h> 37#include <linux/io.h> 38#include <asm/irq.h> 39#include <asm/hardware/arm_timer.h> 40#include <asm/mach-types.h> 41 42#include <asm/mach/arch.h> 43#include <asm/mach/flash.h> 44#include <asm/mach/irq.h> 45#include <asm/mach/time.h> 46#include <asm/mach/map.h> 47 48#include <cfg_global.h> 49 50#include "clock.h" 51 52#include <csp/secHw.h> 53#include <mach/csp/secHw_def.h> 54#include <mach/csp/chipcHw_inline.h> 55#include <mach/csp/tmrHw_reg.h> 56 57#define AMBA_DEVICE(name, initname, base, plat, size) \ 58static struct amba_device name##_device = { \ 59 .dev = { \ 60 .coherent_dma_mask = ~0, \ 61 .init_name = initname, \ 62 .platform_data = plat \ 63 }, \ 64 .res = { \ 65 .start = MM_ADDR_IO_##base, \ 66 .end = MM_ADDR_IO_##base + (size) - 1, \ 67 .flags = IORESOURCE_MEM \ 68 }, \ 69 .dma_mask = ~0, \ 70 .irq = { \ 71 IRQ_##base \ 72 } \ 73} 74 75 76AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K); 77AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K); 78 79static struct clk pll1_clk = { 80 .name = "PLL1", 81 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1, 82 .rate_hz = 2000000000, 83 .use_cnt = 7, 84}; 85 86static struct clk uart_clk = { 87 .name = "UART", 88 .type = CLK_TYPE_PROGRAMMABLE, 89 .csp_id = chipcHw_CLOCK_UART, 90 .rate_hz = HW_CFG_UART_CLK_HZ, 91 .parent = &pll1_clk, 92}; 93 94static struct clk dummy_apb_pclk = { 95 .name = "BUSCLK", 96 .type = CLK_TYPE_PRIMARY, 97 .mode = CLK_MODE_XTAL, 98}; 99 100static struct clk_lookup lookups[] = { 101 { /* Bus clock */ 102 .con_id = "apb_pclk", 103 .clk = &dummy_apb_pclk, 104 }, { /* UART0 */ 105 .dev_id = "uarta", 106 .clk = &uart_clk, 107 }, { /* UART1 */ 108 .dev_id = "uartb", 109 .clk = &uart_clk, 110 } 111}; 112 113static struct amba_device *amba_devs[] __initdata = { 114 &uartA_device, 115 &uartB_device, 116}; 117 118void __init bcmring_amba_init(void) 119{ 120 int i; 121 u32 bus_clock; 122 123/* Linux is run initially in non-secure mode. Secure peripherals */ 124/* generate FIQ, and must be handled in secure mode. Until we have */ 125/* a linux security monitor implementation, keep everything in */ 126/* non-secure mode. */ 127 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU); 128 secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL | 129 secHw_BLK_MASK_KEY_SCAN | 130 secHw_BLK_MASK_TOUCH_SCREEN | 131 secHw_BLK_MASK_UART0 | 132 secHw_BLK_MASK_UART1 | 133 secHw_BLK_MASK_WATCHDOG | 134 secHw_BLK_MASK_SPUM | 135 secHw_BLK_MASK_DDR2 | 136 secHw_BLK_MASK_SPU | 137 secHw_BLK_MASK_PKA | 138 secHw_BLK_MASK_RNG | 139 secHw_BLK_MASK_RTC | 140 secHw_BLK_MASK_OTP | 141 secHw_BLK_MASK_BOOT | 142 secHw_BLK_MASK_MPU | 143 secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR); 144 145 /* Only the devices attached to the AMBA bus are enabled just before the bus is */ 146 /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */ 147 /* driver to access these blocks. The bus is probed, and the drivers are loaded. */ 148 bus_clock = chipcHw_REG_BUS_CLOCK_GE 149 | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1; 150 151 chipcHw_busInterfaceClockEnable(bus_clock); 152 153 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 154 155 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 156 struct amba_device *d = amba_devs[i]; 157 amba_device_register(d, &iomem_resource); 158 } 159} 160 161/* 162 * Where is the timer (VA)? 163 */ 164#define TIMER0_VA_BASE MM_IO_BASE_TMR 165#define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20) 166#define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40) 167#define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60) 168 169/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */ 170#if defined(CONFIG_ARCH_FPGA11107) 171/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */ 172/* slow down Linux's sense of time */ 173#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) 174#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) 175#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30) 176#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30) 177#else 178#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ 179#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ 180#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ 181#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000) 182#endif 183 184#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ 185 186/* 187 * These are useconds NOT ticks. 188 * 189 */ 190#define mSEC_1 1000 191#define mSEC_5 (mSEC_1 * 5) 192#define mSEC_10 (mSEC_1 * 10) 193#define mSEC_25 (mSEC_1 * 25) 194#define SEC_1 (mSEC_1 * 1000) 195 196/* 197 * How long is the timer interval? 198 */ 199#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) 200#if TIMER_INTERVAL >= 0x100000 201#define TIMER_RELOAD (TIMER_INTERVAL >> 8) 202#define TIMER_DIVISOR (TIMER_CTRL_DIV256) 203#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) 204#elif TIMER_INTERVAL >= 0x10000 205#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ 206#define TIMER_DIVISOR (TIMER_CTRL_DIV16) 207#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) 208#else 209#define TIMER_RELOAD (TIMER_INTERVAL) 210#define TIMER_DIVISOR (TIMER_CTRL_DIV1) 211#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) 212#endif 213 214static void timer_set_mode(enum clock_event_mode mode, 215 struct clock_event_device *clk) 216{ 217 unsigned long ctrl; 218 219 switch (mode) { 220 case CLOCK_EVT_MODE_PERIODIC: 221 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); 222 223 ctrl = TIMER_CTRL_PERIODIC; 224 ctrl |= 225 TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE | 226 TIMER_CTRL_ENABLE; 227 break; 228 case CLOCK_EVT_MODE_ONESHOT: 229 /* period set, and timer enabled in 'next_event' hook */ 230 ctrl = TIMER_CTRL_ONESHOT; 231 ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE; 232 break; 233 case CLOCK_EVT_MODE_UNUSED: 234 case CLOCK_EVT_MODE_SHUTDOWN: 235 default: 236 ctrl = 0; 237 } 238 239 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); 240} 241 242static int timer_set_next_event(unsigned long evt, 243 struct clock_event_device *unused) 244{ 245 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); 246 247 writel(evt, TIMER0_VA_BASE + TIMER_LOAD); 248 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); 249 250 return 0; 251} 252 253static struct clock_event_device timer0_clockevent = { 254 .name = "timer0", 255 .shift = 32, 256 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 257 .set_mode = timer_set_mode, 258 .set_next_event = timer_set_next_event, 259}; 260 261/* 262 * IRQ handler for the timer 263 */ 264static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id) 265{ 266 struct clock_event_device *evt = &timer0_clockevent; 267 268 writel(1, TIMER0_VA_BASE + TIMER_INTCLR); 269 270 evt->event_handler(evt); 271 272 return IRQ_HANDLED; 273} 274 275static struct irqaction bcmring_timer_irq = { 276 .name = "bcmring Timer Tick", 277 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 278 .handler = bcmring_timer_interrupt, 279}; 280 281static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs) 282{ 283 return ~readl(TIMER1_VA_BASE + TIMER_VALUE); 284} 285 286static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs) 287{ 288 return ~readl(TIMER3_VA_BASE + TIMER_VALUE); 289} 290 291static struct clocksource clocksource_bcmring_timer1 = { 292 .name = "timer1", 293 .rating = 200, 294 .read = bcmring_get_cycles_timer1, 295 .mask = CLOCKSOURCE_MASK(32), 296 .shift = 20, 297 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 298}; 299 300static struct clocksource clocksource_bcmring_timer3 = { 301 .name = "timer3", 302 .rating = 100, 303 .read = bcmring_get_cycles_timer3, 304 .mask = CLOCKSOURCE_MASK(32), 305 .shift = 20, 306 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 307}; 308 309static int __init bcmring_clocksource_init(void) 310{ 311 /* setup timer1 as free-running clocksource */ 312 writel(0, TIMER1_VA_BASE + TIMER_CTRL); 313 writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD); 314 writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE); 315 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, 316 TIMER1_VA_BASE + TIMER_CTRL); 317 318 clocksource_bcmring_timer1.mult = 319 clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000, 320 clocksource_bcmring_timer1.shift); 321 clocksource_register(&clocksource_bcmring_timer1); 322 323 /* setup timer3 as free-running clocksource */ 324 writel(0, TIMER3_VA_BASE + TIMER_CTRL); 325 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); 326 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); 327 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, 328 TIMER3_VA_BASE + TIMER_CTRL); 329 330 clocksource_bcmring_timer3.mult = 331 clocksource_khz2mult(TIMER3_FREQUENCY_KHZ, 332 clocksource_bcmring_timer3.shift); 333 clocksource_register(&clocksource_bcmring_timer3); 334 335 return 0; 336} 337 338/* 339 * Set up timer interrupt, and return the current time in seconds. 340 */ 341void __init bcmring_init_timer(void) 342{ 343 printk(KERN_INFO "bcmring_init_timer\n"); 344 /* 345 * Initialise to a known state (all timers off) 346 */ 347 writel(0, TIMER0_VA_BASE + TIMER_CTRL); 348 writel(0, TIMER1_VA_BASE + TIMER_CTRL); 349 writel(0, TIMER2_VA_BASE + TIMER_CTRL); 350 writel(0, TIMER3_VA_BASE + TIMER_CTRL); 351 352 /* 353 * Make irqs happen for the system timer 354 */ 355 setup_irq(IRQ_TIMER0, &bcmring_timer_irq); 356 357 bcmring_clocksource_init(); 358 359 timer0_clockevent.mult = 360 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); 361 timer0_clockevent.max_delta_ns = 362 clockevent_delta2ns(0xffffffff, &timer0_clockevent); 363 timer0_clockevent.min_delta_ns = 364 clockevent_delta2ns(0xf, &timer0_clockevent); 365 366 timer0_clockevent.cpumask = cpumask_of(0); 367 clockevents_register_device(&timer0_clockevent); 368} 369 370struct sys_timer bcmring_timer = { 371 .init = bcmring_init_timer, 372}; 373