Searched refs:TIMER1_2_CONTROL_OFFSET (Results 1 - 4 of 4) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-cns3xxx/ |
| H A D | core.c | 103 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
123 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
129 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
132 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
198 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
216 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
218 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
230 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
232 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-cns3xxx/ |
| H A D | core.c | 103 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
123 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
129 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
132 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
198 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
216 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
218 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
230 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
232 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-cns3xxx/include/mach/ |
| H A D | cns3xxx.h | 145 #define TIMER1_2_CONTROL_OFFSET 0x30 macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-cns3xxx/include/mach/ |
| H A D | cns3xxx.h | 145 #define TIMER1_2_CONTROL_OFFSET 0x30 macro
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