1/* 2 * Copyright 2008 Cavium Networks 3 * 4 * This file is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License, Version 2, as 6 * published by the Free Software Foundation. 7 */ 8 9#ifndef __MACH_BOARD_CNS3XXXH 10#define __MACH_BOARD_CNS3XXXH 11 12/* 13 * Memory map 14 */ 15#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ 16#define CNS3XXX_FLASH_SIZE SZ_256M 17 18#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ 19 20#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ 21 22#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ 23#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 24 25#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ 26#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 27 28#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ 29#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 30 31#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ 32#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 33 34#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ 35#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 36 37#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ 38#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 39 40#define SMC_MEMC_STATUS_OFFSET 0x000 41#define SMC_MEMIF_CFG_OFFSET 0x004 42#define SMC_MEMC_CFG_SET_OFFSET 0x008 43#define SMC_MEMC_CFG_CLR_OFFSET 0x00C 44#define SMC_DIRECT_CMD_OFFSET 0x010 45#define SMC_SET_CYCLES_OFFSET 0x014 46#define SMC_SET_OPMODE_OFFSET 0x018 47#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 48#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 49#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 50#define SMC_NAND_CYCLES0_0_OFFSET 0x100 51#define SMC_OPMODE0_0_OFFSET 0x104 52#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 53#define SMC_NAND_CYCLES0_1_OFFSET 0x120 54#define SMC_OPMODE0_1_OFFSET 0x124 55#define SMC_USER_STATUS_OFFSET 0x200 56#define SMC_USER_CONFIG_OFFSET 0x204 57#define SMC_ECC_STATUS_OFFSET 0x300 58#define SMC_ECC_MEMCFG_OFFSET 0x304 59#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 60#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C 61#define SMC_ECC_ADDR0_OFFSET 0x310 62#define SMC_ECC_ADDR1_OFFSET 0x314 63#define SMC_ECC_VALUE0_OFFSET 0x318 64#define SMC_ECC_VALUE1_OFFSET 0x31C 65#define SMC_ECC_VALUE2_OFFSET 0x320 66#define SMC_ECC_VALUE3_OFFSET 0x324 67#define SMC_PERIPH_ID_0_OFFSET 0xFE0 68#define SMC_PERIPH_ID_1_OFFSET 0xFE4 69#define SMC_PERIPH_ID_2_OFFSET 0xFE8 70#define SMC_PERIPH_ID_3_OFFSET 0xFEC 71#define SMC_PCELL_ID_0_OFFSET 0xFF0 72#define SMC_PCELL_ID_1_OFFSET 0xFF4 73#define SMC_PCELL_ID_2_OFFSET 0xFF8 74#define SMC_PCELL_ID_3_OFFSET 0xFFC 75 76#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ 77#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 78 79#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ 80#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 81 82#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ 83#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 84 85#define RTC_SEC_OFFSET 0x00 86#define RTC_MIN_OFFSET 0x04 87#define RTC_HOUR_OFFSET 0x08 88#define RTC_DAY_OFFSET 0x0C 89#define RTC_SEC_ALM_OFFSET 0x10 90#define RTC_MIN_ALM_OFFSET 0x14 91#define RTC_HOUR_ALM_OFFSET 0x18 92#define RTC_REC_OFFSET 0x1C 93#define RTC_CTRL_OFFSET 0x20 94#define RTC_INTR_STS_OFFSET 0x34 95 96#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ 97#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ 98 99#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ 100#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 101 102#define PM_CLK_GATE_OFFSET 0x00 103#define PM_SOFT_RST_OFFSET 0x04 104#define PM_HS_CFG_OFFSET 0x08 105#define PM_CACTIVE_STA_OFFSET 0x0C 106#define PM_PWR_STA_OFFSET 0x10 107#define PM_SYS_CLK_CTRL_OFFSET 0x14 108#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 109#define PM_PLL_HM_PD_OFFSET 0x1C 110 111#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ 112#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 113 114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ 115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 116 117#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ 118#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 119 120#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ 121#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 122 123#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ 124#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 125 126#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ 127#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 128 129#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ 130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 131 132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ 133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 134 135#define TIMER1_COUNTER_OFFSET 0x00 136#define TIMER1_AUTO_RELOAD_OFFSET 0x04 137#define TIMER1_MATCH_V1_OFFSET 0x08 138#define TIMER1_MATCH_V2_OFFSET 0x0C 139 140#define TIMER2_COUNTER_OFFSET 0x10 141#define TIMER2_AUTO_RELOAD_OFFSET 0x14 142#define TIMER2_MATCH_V1_OFFSET 0x18 143#define TIMER2_MATCH_V2_OFFSET 0x1C 144 145#define TIMER1_2_CONTROL_OFFSET 0x30 146#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 147#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 148 149#define TIMER_FREERUN_OFFSET 0x40 150#define TIMER_FREERUN_CONTROL_OFFSET 0x44 151 152#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ 153#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 154 155#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ 156#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 157 158#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ 159#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 160 161#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ 162#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 163 164#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ 165#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 166 167#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ 168#define CNS3XXX_USB_BASE_VIRT 0xFFF16000 169 170#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ 171#define CNS3XXX_SATA2_SIZE SZ_16M 172#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 173 174#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ 175#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 176 177#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ 178#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 179 180#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ 181#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 182 183#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ 184#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 185 186#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ 187#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000 188 189#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ 190#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 191 192#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ 193#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 194 195#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ 196#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 197 198#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ 199#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 200 201#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ 202#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 203 204#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ 205#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 206 207#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ 208#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 209 210#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ 211#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 212 213#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ 214#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 215 216#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ 217#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 218 219#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ 220#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 221 222#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ 223#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 224 225#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ 226#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 227 228/* 229 * Testchip peripheral and fpga gic regions 230 */ 231#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ 232#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 233 234#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ 235#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 236 237#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 238#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 239 240#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ 241#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 242 243#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ 244#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 245 246/* 247 * Misc block 248 */ 249#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) 250 251#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) 252#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) 253#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) 254#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) 255#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) 256#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) 257#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) 258#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) 259#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) 260#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) 261#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) 262#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) 263#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) 264#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) 265#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) 266#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) 267#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) 268#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) 269#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) 270#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) 271 272#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) 273 274#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) 275#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) 276#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) 277#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) 278#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) 279#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) 280 281#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) 282#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) 283#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) 284#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) 285#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) 286#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) 287#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) 288#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) 289#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) 290#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) 291#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) 292#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) 293#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) 294#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) 295#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) 296#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) 297#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) 298 299/* 300 * Power management and clock control 301 */ 302#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) 303 304#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) 305#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) 306#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) 307#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) 308#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) 309#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) 310#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) 311#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) 312#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) 313#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) 314#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) 315#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) 316#define PM_CSR_REG PMU_MEM_MAP(0x030) 317 318/* PM_CLK_GATE_REG */ 319#define PM_CLK_GATE_REG_OFFSET_SDIO (25) 320#define PM_CLK_GATE_REG_OFFSET_GPU (24) 321#define PM_CLK_GATE_REG_OFFSET_CIM (23) 322#define PM_CLK_GATE_REG_OFFSET_LCDC (22) 323#define PM_CLK_GATE_REG_OFFSET_I2S (21) 324#define PM_CLK_GATE_REG_OFFSET_RAID (20) 325#define PM_CLK_GATE_REG_OFFSET_SATA (19) 326#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) 327#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) 328#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) 329#define PM_CLK_GATE_REG_OFFSET_TIMER (14) 330#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) 331#define PM_CLK_GATE_REG_OFFSET_HCIE (12) 332#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) 333#define PM_CLK_GATE_REG_OFFSET_GPIO (10) 334#define PM_CLK_GATE_REG_OFFSET_UART3 (9) 335#define PM_CLK_GATE_REG_OFFSET_UART2 (8) 336#define PM_CLK_GATE_REG_OFFSET_UART1 (7) 337#define PM_CLK_GATE_REG_OFFSET_RTC (5) 338#define PM_CLK_GATE_REG_OFFSET_GDMA (4) 339#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) 340#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) 341#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) 342 343/* PM_SOFT_RST_REG */ 344#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) 345#define PM_SOFT_RST_REG_OFFST_CPU1 (29) 346#define PM_SOFT_RST_REG_OFFST_CPU0 (28) 347#define PM_SOFT_RST_REG_OFFST_SDIO (25) 348#define PM_SOFT_RST_REG_OFFST_GPU (24) 349#define PM_SOFT_RST_REG_OFFST_CIM (23) 350#define PM_SOFT_RST_REG_OFFST_LCDC (22) 351#define PM_SOFT_RST_REG_OFFST_I2S (21) 352#define PM_SOFT_RST_REG_OFFST_RAID (20) 353#define PM_SOFT_RST_REG_OFFST_SATA (19) 354#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) 355#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) 356#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) 357#define PM_SOFT_RST_REG_OFFST_TIMER (14) 358#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) 359#define PM_SOFT_RST_REG_OFFST_HCIE (12) 360#define PM_SOFT_RST_REG_OFFST_SWITCH (11) 361#define PM_SOFT_RST_REG_OFFST_GPIO (10) 362#define PM_SOFT_RST_REG_OFFST_UART3 (9) 363#define PM_SOFT_RST_REG_OFFST_UART2 (8) 364#define PM_SOFT_RST_REG_OFFST_UART1 (7) 365#define PM_SOFT_RST_REG_OFFST_RTC (5) 366#define PM_SOFT_RST_REG_OFFST_GDMA (4) 367#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) 368#define PM_SOFT_RST_REG_OFFST_DMC (2) 369#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) 370#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) 371#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) 372 373/* PMHS_CFG_REG */ 374#define PM_HS_CFG_REG_OFFSET_SDIO (25) 375#define PM_HS_CFG_REG_OFFSET_GPU (24) 376#define PM_HS_CFG_REG_OFFSET_CIM (23) 377#define PM_HS_CFG_REG_OFFSET_LCDC (22) 378#define PM_HS_CFG_REG_OFFSET_I2S (21) 379#define PM_HS_CFG_REG_OFFSET_RAID (20) 380#define PM_HS_CFG_REG_OFFSET_SATA (19) 381#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) 382#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) 383#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) 384#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) 385#define PM_HS_CFG_REG_OFFSET_TIMER (14) 386#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) 387#define PM_HS_CFG_REG_OFFSET_HCIE (12) 388#define PM_HS_CFG_REG_OFFSET_SWITCH (11) 389#define PM_HS_CFG_REG_OFFSET_GPIO (10) 390#define PM_HS_CFG_REG_OFFSET_UART3 (9) 391#define PM_HS_CFG_REG_OFFSET_UART2 (8) 392#define PM_HS_CFG_REG_OFFSET_UART1 (7) 393#define PM_HS_CFG_REG_OFFSET_RTC (5) 394#define PM_HS_CFG_REG_OFFSET_GDMA (4) 395#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) 396#define PM_HS_CFG_REG_OFFSET_DMC (2) 397#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) 398#define PM_HS_CFG_REG_MASK (0x03FFFFBE) 399#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) 400 401/* PM_CACTIVE_STA_REG */ 402#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) 403#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) 404#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) 405#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) 406#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) 407#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) 408#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) 409#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) 410#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) 411#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) 412#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) 413#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) 414#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) 415#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) 416#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) 417#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) 418#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) 419#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) 420#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) 421#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) 422#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) 423#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) 424#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) 425#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) 426#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) 427 428/* PM_PWR_STA_REG */ 429#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) 430#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) 431#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) 432#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) 433#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) 434#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) 435#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) 436#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) 437#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) 438#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) 439#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) 440#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) 441#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) 442#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) 443#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) 444#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) 445#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) 446#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) 447#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) 448#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) 449#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) 450#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) 451#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) 452#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) 453#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) 454 455/* PM_CLK_CTRL_REG */ 456#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) 457#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) 458#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) 459#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) 460#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) 461#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) 462#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) 463#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) 464#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) 465#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) 466#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) 467#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) 468#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) 469#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) 470#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) 471#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) 472 473#define PM_CPU_CLK_DIV(DIV) { \ 474 PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ 475 PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ 476} 477 478#define PM_PLL_CPU_SEL(CPU) { \ 479 PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ 480 PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ 481} 482 483/* PM_PLL_LCD_I2S_CTRL_REG */ 484#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) 485#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) 486#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) 487#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) 488#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) 489 490/* PM_PLL_HM_PD_CTRL_REG */ 491#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) 492#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) 493#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) 494#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) 495#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) 496#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) 497#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) 498#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) 499 500/* PM_WDT_CTRL_REG */ 501#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) 502 503/* PM_CSR_REG - Clock Scaling Register*/ 504#define PM_CSR_REG_OFFSET_CSR_EN (30) 505#define PM_CSR_REG_OFFSET_CSR_NUM (0) 506 507#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK) 508 509/* Software reset*/ 510#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK) 511 512/* 513 * CNS3XXX support several power saving mode as following, 514 * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate 515 */ 516#define CNS3XXX_PWR_CPU_MODE_DFS (0) 517#define CNS3XXX_PWR_CPU_MODE_IDLE (1) 518#define CNS3XXX_PWR_CPU_MODE_HALT (2) 519#define CNS3XXX_PWR_CPU_MODE_DOZE (3) 520#define CNS3XXX_PWR_CPU_MODE_SLEEP (4) 521#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5) 522 523#define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK) 524#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK 525 526/* Change CPU frequency and divider */ 527#define CNS3XXX_PWR_PLL_CPU_300MHZ (0) 528#define CNS3XXX_PWR_PLL_CPU_333MHZ (1) 529#define CNS3XXX_PWR_PLL_CPU_366MHZ (2) 530#define CNS3XXX_PWR_PLL_CPU_400MHZ (3) 531#define CNS3XXX_PWR_PLL_CPU_433MHZ (4) 532#define CNS3XXX_PWR_PLL_CPU_466MHZ (5) 533#define CNS3XXX_PWR_PLL_CPU_500MHZ (6) 534#define CNS3XXX_PWR_PLL_CPU_533MHZ (7) 535#define CNS3XXX_PWR_PLL_CPU_566MHZ (8) 536#define CNS3XXX_PWR_PLL_CPU_600MHZ (9) 537#define CNS3XXX_PWR_PLL_CPU_633MHZ (10) 538#define CNS3XXX_PWR_PLL_CPU_666MHZ (11) 539#define CNS3XXX_PWR_PLL_CPU_700MHZ (12) 540 541#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0) 542#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1) 543#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2) 544 545/* Change DDR2 frequency */ 546#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0) 547#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1) 548#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2) 549#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3) 550 551void cns3xxx_pwr_soft_rst(unsigned int block); 552void cns3xxx_pwr_clk_en(unsigned int block); 553int cns3xxx_cpu_clock(void); 554 555/* 556 * ARM11 MPCore interrupt sources (primary GIC) 557 */ 558#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0) 559#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1) 560#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2) 561#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3) 562#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4) 563#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5) 564#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6) 565#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7) 566#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8) 567#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9) 568#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10) 569#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11) 570#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12) 571#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13) 572#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14) 573#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15) 574#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16) 575 576#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17) 577#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18) 578#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19) 579#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20) 580#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21) 581#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22) 582#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23) 583#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24) 584#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25) 585#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26) 586 587#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27) 588#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28) 589#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29) 590#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30) 591#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31) 592#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32) 593#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33) 594#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34) 595#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35) 596 597#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36) 598#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37) 599#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38) 600#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39) 601#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40) 602#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41) 603#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42) 604#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43) 605#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44) 606#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45) 607#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46) 608#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47) 609#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48) 610#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49) 611#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50) 612#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51) 613#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52) 614#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53) 615#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54) 616 617#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55) 618#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56) 619#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57) 620#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58) 621#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59) 622#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60) 623#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61) 624#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62) 625#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63) 626 627#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64) 628 629#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX) 630#undef NR_IRQS 631#define NR_IRQS NR_IRQS_CNS3XXX 632#endif 633 634#endif /* __MACH_BOARD_CNS3XXX_H */ 635