Searched refs:TIMER1CTRL (Results 1 - 2 of 2) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/msm/ |
| H A D | mddi_toshiba.c | 89 #define TIMER1CTRL (PWM_BLOCK_BASE|0x28) macro
579 write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
583 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
667 write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
674 write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
680 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
1274 write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
1278 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/msm/ |
| H A D | mddi_toshiba.c | 89 #define TIMER1CTRL (PWM_BLOCK_BASE|0x28) macro
579 write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
583 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
667 write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
674 write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
680 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
1274 write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
1278 write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
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Completed in 287 milliseconds