Searched refs:SPORT2_RCLKDIV (Results 1 - 8 of 8) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h328 #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
329 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
H A DdefBF539.h816 #define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h328 #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
329 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
H A DdefBF539.h816 #define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h982 #define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */ macro
H A DcdefBF54x_base.h1685 #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
1686 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h982 #define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */ macro
H A DcdefBF54x_base.h1685 #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
1686 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)

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