Searched refs:SICB_IMASK0 (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf561/include/mach/
H A Dblackfin.h44 #define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
45 #define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
H A DdefBF561.h62 #define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ macro
H A DcdefBF561.h84 #define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
85 #define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A Dblackfin.h44 #define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
45 #define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
H A DdefBF561.h62 #define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ macro
H A DcdefBF561.h84 #define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
85 #define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)

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