1/* 2 * Copyright 2005-2009 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later. 5 */ 6 7#ifndef _MACH_BLACKFIN_H_ 8#define _MACH_BLACKFIN_H_ 9 10#define BF561_FAMILY 11 12#include "bf561.h" 13#include "defBF561.h" 14#include "anomaly.h" 15 16#if !defined(__ASSEMBLY__) 17#include "cdefBF561.h" 18#endif 19 20#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D() 21#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val) 22#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR() 23#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val) 24#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() 25#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 26 27#define SIC_IWR0 SICA_IWR0 28#define SIC_IWR1 SICA_IWR1 29#define SIC_IAR0 SICA_IAR0 30#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 31#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 32#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 33#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 34 35#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 36#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 37#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0 38#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1 39#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0 40#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1 41 42#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) 43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) 44#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2)) 45#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val) 46#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) 47#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) 48#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2)) 49#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val) 50 51#define BFIN_UART_NR_PORTS 1 52 53#define OFFSET_THR 0x00 /* Transmit Holding register */ 54#define OFFSET_RBR 0x00 /* Receive Buffer register */ 55#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 56#define OFFSET_IER 0x04 /* Interrupt Enable Register */ 57#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ 58#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ 59#define OFFSET_LCR 0x0C /* Line Control Register */ 60#define OFFSET_MCR 0x10 /* Modem Control Register */ 61#define OFFSET_LSR 0x14 /* Line Status Register */ 62#define OFFSET_MSR 0x18 /* Modem Status Register */ 63#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 64#define OFFSET_GCTL 0x24 /* Global Control Register */ 65 66#endif /* _MACH_BLACKFIN_H_ */ 67