| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-shmobile/ |
| H A D | intc-sh7367.c | 47 SCIFA0, SCIFA1, SCIFA2, SCIFA3, enumerator in enum:__anon11883
104 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
187 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
231 SCIFA2, SCIFA3 } },
|
| H A D | intc-sh7372.c | 48 SCIFA0, SCIFA1, SCIFA2, SCIFA3, enumerator in enum:__anon11885
122 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
228 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
301 SCIFA2, SCIFA3 } },
|
| H A D | intc-sh7377.c | 50 SCIFA0, SCIFA1, SCIFA2, SCIFA3, enumerator in enum:__anon11887
127 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
232 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
296 SCIFA2, SCIFA3 } },
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-shmobile/ |
| H A D | intc-sh7367.c | 47 SCIFA0, SCIFA1, SCIFA2, SCIFA3, enumerator in enum:__anon23576
104 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
187 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
231 SCIFA2, SCIFA3 } },
|
| H A D | intc-sh7372.c | 48 SCIFA0, SCIFA1, SCIFA2, SCIFA3, enumerator in enum:__anon23578
122 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
228 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
301 SCIFA2, SCIFA3 } },
|
| H A D | intc-sh7377.c | 50 SCIFA0, SCIFA1, SCIFA2, SCIFA3, enumerator in enum:__anon23580
127 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
232 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
296 SCIFA2, SCIFA3 } },
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/ |
| H A D | setup-sh7724.c | 923 SCIFA3, enumerator in enum:__anon25814
985 INTC_VECT(SCIFA3, 0x900),
1086 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1126 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/kernel/cpu/sh4a/ |
| H A D | setup-sh7724.c | 923 SCIFA3, enumerator in enum:__anon14121
985 INTC_VECT(SCIFA3, 0x900),
1086 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1126 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
|