Searched refs:PLLCTL (Results 1 - 14 of 14) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-davinci/
H A Dpm.c45 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
47 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
52 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
54 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
69 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
71 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
74 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
76 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
82 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
84 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
[all...]
H A Dsleep.S90 ldr ip, [r3, #PLLCTL]
93 str ip, [r3, #PLLCTL]
101 ldr ip, [r3, #PLLCTL]
103 str ip, [r3, #PLLCTL]
121 ldr ip, [r3, #PLLCTL]
123 str ip, [r3, #PLLCTL]
126 ldr ip, [r3, #PLLCTL]
128 str ip, [r3, #PLLCTL]
135 ldr ip, [r3, #PLLCTL]
137 str ip, [r3, #PLLCTL]
[all...]
H A Dclock.c305 ctrl = __raw_readl(pll->base + PLLCTL);
398 ctrl = __raw_readl(pll->base + PLLCTL);
402 __raw_writel(ctrl, pll->base + PLLCTL);
408 __raw_writel(ctrl, pll->base + PLLCTL);
422 __raw_writel(ctrl, pll->base + PLLCTL);
428 __raw_writel(ctrl, pll->base + PLLCTL);
H A Dclock.h20 #define PLLCTL 0x100 macro
H A Dtnetv107x.c670 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
676 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-davinci/
H A Dpm.c45 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
47 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
52 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
54 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
69 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
71 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
74 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
76 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
82 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
84 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
[all...]
H A Dsleep.S90 ldr ip, [r3, #PLLCTL]
93 str ip, [r3, #PLLCTL]
101 ldr ip, [r3, #PLLCTL]
103 str ip, [r3, #PLLCTL]
121 ldr ip, [r3, #PLLCTL]
123 str ip, [r3, #PLLCTL]
126 ldr ip, [r3, #PLLCTL]
128 str ip, [r3, #PLLCTL]
135 ldr ip, [r3, #PLLCTL]
137 str ip, [r3, #PLLCTL]
[all...]
H A Dclock.c305 ctrl = __raw_readl(pll->base + PLLCTL);
398 ctrl = __raw_readl(pll->base + PLLCTL);
402 __raw_writel(ctrl, pll->base + PLLCTL);
408 __raw_writel(ctrl, pll->base + PLLCTL);
422 __raw_writel(ctrl, pll->base + PLLCTL);
428 __raw_writel(ctrl, pll->base + PLLCTL);
H A Dclock.h20 #define PLLCTL 0x100 macro
H A Dtnetv107x.c670 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
676 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/pci/ctxfi/
H A Dcthw20k1.c1318 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1321 hw_write_20kx(hw, PLLCTL, pllctl);
1959 data = hw_read_20kx(hw, PLLCTL);
1960 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
H A Dct20k1reg.h615 #define PLLCTL 0x1C6060 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/sound/pci/ctxfi/
H A Dcthw20k1.c1318 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1321 hw_write_20kx(hw, PLLCTL, pllctl);
1959 data = hw_read_20kx(hw, PLLCTL);
1960 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
H A Dct20k1reg.h615 #define PLLCTL 0x1C6060 macro

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