Searched refs:PHY_REG (Results 1 - 20 of 20) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/e1000e/
H A De1000.h104 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
105 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
106 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
107 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
122 #define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
123 #define HV_SCC_LOWER PHY_REG(778, 17)
124 #define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
125 #define HV_ECOL_LOWER PHY_REG(778, 19)
126 #define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
127 #define HV_MCC_LOWER PHY_REG(77
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H A Dich8lan.c117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
137 #define HV_PM_CTRL PHY_REG(770, 17)
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
149 #define HV_OEM_BITS PHY_REG(768, 25)
158 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
1114 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(77
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H A Dethtool.c1302 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg);
1305 e1e_wphy(hw, PHY_REG(2, 21), phy_reg);
1310 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
1311 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C);
1313 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg);
1314 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040);
1316 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
1317 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040);
1319 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1320 e1e_wphy(hw, PHY_REG(76
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H A Dhw.h249 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
250 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
251 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
H A Ddefines.h784 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
H A Dphy.c99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
H A Dnetdev.c2721 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2724 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/e1000e/
H A De1000.h104 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
105 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
106 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
107 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
122 #define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
123 #define HV_SCC_LOWER PHY_REG(778, 17)
124 #define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
125 #define HV_ECOL_LOWER PHY_REG(778, 19)
126 #define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
127 #define HV_MCC_LOWER PHY_REG(77
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H A Dich8lan.c117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
137 #define HV_PM_CTRL PHY_REG(770, 17)
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
149 #define HV_OEM_BITS PHY_REG(768, 25)
158 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
1114 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(77
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H A Dethtool.c1302 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg);
1305 e1e_wphy(hw, PHY_REG(2, 21), phy_reg);
1310 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
1311 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C);
1313 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg);
1314 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040);
1316 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
1317 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040);
1319 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1320 e1e_wphy(hw, PHY_REG(76
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H A Dhw.h249 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
250 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
251 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
H A Ddefines.h784 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
H A Dphy.c99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
H A Dnetdev.c2721 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2724 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/e1000/
H A De1000_hw.h2879 #define PHY_REG(page, reg) \ macro
2883 PHY_REG(769, 17) /* Port General Configuration */
2885 PHY_REG(769, 25) /* Rate Adapter Control Register */
2888 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2890 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2892 PHY_REG(770, 18) /* KMRN Inband Control Register */
2894 PHY_REG(770, 19) /* KMRN Diagnostic register */
2897 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2900 PHY_REG(776, 18) /* Voltage regulator control register */
2905 PHY_REG(77
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/e1000/
H A De1000_hw.h2879 #define PHY_REG(page, reg) \ macro
2883 PHY_REG(769, 17) /* Port General Configuration */
2885 PHY_REG(769, 25) /* Rate Adapter Control Register */
2888 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2890 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2892 PHY_REG(770, 18) /* KMRN Inband Control Register */
2894 PHY_REG(770, 19) /* KMRN Diagnostic register */
2897 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2900 PHY_REG(776, 18) /* Voltage regulator control register */
2905 PHY_REG(77
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192S_hw.h408 #define PHY_REG 0x02F3 // RPT: PHY REG Access Report Reg[7:0] macro
H A Dr8192S_phy.c112 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
763 // 1. Read PHY_REG.TXT BB INIT!!
771 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/
H A Dr8192S_hw.h408 #define PHY_REG 0x02F3 // RPT: PHY REG Access Report Reg[7:0] macro
H A Dr8192S_phy.c112 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
763 // 1. Read PHY_REG.TXT BB INIT!!
771 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,

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