Searched refs:PHASE_SR_TO_TCR (Results 1 - 16 of 16) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/ |
| H A D | mac_scsi.c | 326 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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| H A D | NCR5380.h | 211 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2) macro
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| H A D | sun3_scsi.c | 341 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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| H A D | sun3_scsi_vme.c | 310 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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| H A D | sun3_NCR5380.c | 1572 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1695 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1849 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
2365 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(PHASE_MSGIN));
2673 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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| H A D | NCR5380.c | 1491 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1607 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));
1642 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1717 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1921 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
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| H A D | atari_NCR5380.c | 1584 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1710 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1778 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1842 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
2661 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG)));
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| H A D | atari_scsi.c | 806 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG)));
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/ |
| H A D | NCR5380.h | 211 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2) macro
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| H A D | mac_scsi.c | 326 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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| H A D | sun3_scsi.c | 341 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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| H A D | sun3_scsi_vme.c | 310 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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| H A D | NCR5380.c | 1491 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1607 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));
1642 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1717 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1921 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
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| H A D | sun3_NCR5380.c | 1572 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1695 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1849 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
2365 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(PHASE_MSGIN));
2673 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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| H A D | atari_NCR5380.c | 1584 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1710 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1778 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1842 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
2661 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG)));
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| H A D | atari_scsi.c | 806 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG)));
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