1/* 2 * NCR 5380 defines 3 * 4 * Copyright 1993, Drew Eckhardt 5 * Visionary Computing 6 * (Unix consulting and custom programming) 7 * drew@colorado.edu 8 * +1 (303) 666-5836 9 * 10 * DISTRIBUTION RELEASE 7 11 * 12 * For more information, please consult 13 * 14 * NCR 5380 Family 15 * SCSI Protocol Controller 16 * Databook 17 * NCR Microelectronics 18 * 1635 Aeroplaza Drive 19 * Colorado Springs, CO 80916 20 * 1+ (719) 578-3400 21 * 1+ (800) 334-5454 22 */ 23 24/* 25 * $Log: NCR5380.h,v $ 26 */ 27 28#ifndef NCR5380_H 29#define NCR5380_H 30 31#include <linux/interrupt.h> 32 33#ifdef AUTOSENSE 34#include <scsi/scsi_eh.h> 35#endif 36 37#define NCR5380_PUBLIC_RELEASE 7 38#define NCR53C400_PUBLIC_RELEASE 2 39 40#define NDEBUG_ARBITRATION 0x1 41#define NDEBUG_AUTOSENSE 0x2 42#define NDEBUG_DMA 0x4 43#define NDEBUG_HANDSHAKE 0x8 44#define NDEBUG_INFORMATION 0x10 45#define NDEBUG_INIT 0x20 46#define NDEBUG_INTR 0x40 47#define NDEBUG_LINKED 0x80 48#define NDEBUG_MAIN 0x100 49#define NDEBUG_NO_DATAOUT 0x200 50#define NDEBUG_NO_WRITE 0x400 51#define NDEBUG_PIO 0x800 52#define NDEBUG_PSEUDO_DMA 0x1000 53#define NDEBUG_QUEUES 0x2000 54#define NDEBUG_RESELECTION 0x4000 55#define NDEBUG_SELECTION 0x8000 56#define NDEBUG_USLEEP 0x10000 57#define NDEBUG_LAST_BYTE_SENT 0x20000 58#define NDEBUG_RESTART_SELECT 0x40000 59#define NDEBUG_EXTENDED 0x80000 60#define NDEBUG_C400_PREAD 0x100000 61#define NDEBUG_C400_PWRITE 0x200000 62#define NDEBUG_LISTS 0x400000 63 64#define NDEBUG_ANY 0xFFFFFFFFUL 65 66/* 67 * The contents of the OUTPUT DATA register are asserted on the bus when 68 * either arbitration is occurring or the phase-indicating signals ( 69 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA 70 * bit in the INITIATOR COMMAND register is set. 71 */ 72 73#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */ 74#define CURRENT_SCSI_DATA_REG 0 /* ro same */ 75 76#define INITIATOR_COMMAND_REG 1 /* rw */ 77#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */ 78#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */ 79#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */ 80#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */ 81#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */ 82#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */ 83#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */ 84#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */ 85#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */ 86#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */ 87 88#ifdef DIFFERENTIAL 89#define ICR_BASE ICR_DIFF_ENABLE 90#else 91#define ICR_BASE 0 92#endif 93 94#define MODE_REG 2 95/* 96 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 97 * transfer, causing the chip to hog the bus. You probably don't want 98 * this. 99 */ 100#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */ 101#define MR_TARGET 0x40 /* rw target mode */ 102#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */ 103#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */ 104#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */ 105#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */ 106#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */ 107#define MR_ARBITRATE 0x01 /* rw start arbitration */ 108 109#ifdef PARITY 110#define MR_BASE MR_ENABLE_PAR_CHECK 111#else 112#define MR_BASE 0 113#endif 114 115#define TARGET_COMMAND_REG 3 116#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */ 117#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */ 118#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */ 119#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */ 120#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */ 121 122#define STATUS_REG 4 /* ro */ 123/* 124 * Note : a set bit indicates an active signal, driven by us or another 125 * device. 126 */ 127#define SR_RST 0x80 128#define SR_BSY 0x40 129#define SR_REQ 0x20 130#define SR_MSG 0x10 131#define SR_CD 0x08 132#define SR_IO 0x04 133#define SR_SEL 0x02 134#define SR_DBP 0x01 135 136/* 137 * Setting a bit in this register will cause an interrupt to be generated when 138 * BSY is false and SEL true and this bit is asserted on the bus. 139 */ 140#define SELECT_ENABLE_REG 4 /* wo */ 141 142#define BUS_AND_STATUS_REG 5 /* ro */ 143#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */ 144#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */ 145#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */ 146#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */ 147#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */ 148#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */ 149#define BASR_ATN 0x02 /* ro BUS status */ 150#define BASR_ACK 0x01 /* ro BUS status */ 151 152/* Write any value to this register to start a DMA send */ 153#define START_DMA_SEND_REG 5 /* wo */ 154 155/* 156 * Used in DMA transfer mode, data is latched from the SCSI bus on 157 * the falling edge of REQ (ini) or ACK (tgt) 158 */ 159#define INPUT_DATA_REG 6 /* ro */ 160 161/* Write any value to this register to start a DMA receive */ 162#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */ 163 164/* Read this register to clear interrupt conditions */ 165#define RESET_PARITY_INTERRUPT_REG 7 /* ro */ 166 167/* Write any value to this register to start an ini mode DMA receive */ 168#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */ 169 170#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */ 171 172#define CSR_RESET 0x80 /* wo Resets 53c400 */ 173#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */ 174#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */ 175#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */ 176#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */ 177#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */ 178#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */ 179#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */ 180#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */ 181 182#define CSR_BASE CSR_53C80_INTR 183 184/* Number of 128-byte blocks to be transferred */ 185#define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */ 186 187/* Resume transfer after disconnect */ 188#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */ 189 190/* Access to host buffer stack */ 191#define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */ 192 193 194/* Note : PHASE_* macros are based on the values of the STATUS register */ 195#define PHASE_MASK (SR_MSG | SR_CD | SR_IO) 196 197#define PHASE_DATAOUT 0 198#define PHASE_DATAIN SR_IO 199#define PHASE_CMDOUT SR_CD 200#define PHASE_STATIN (SR_CD | SR_IO) 201#define PHASE_MSGOUT (SR_MSG | SR_CD) 202#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO) 203#define PHASE_UNKNOWN 0xff 204 205/* 206 * Convert status register phase to something we can use to set phase in 207 * the target register so we can get phase mismatch interrupts on DMA 208 * transfers. 209 */ 210 211#define PHASE_SR_TO_TCR(phase) ((phase) >> 2) 212 213/* 214 * The internal should_disconnect() function returns these based on the 215 * expected length of a disconnect if a device supports disconnect/ 216 * reconnect. 217 */ 218 219#define DISCONNECT_NONE 0 220#define DISCONNECT_TIME_TO_DATA 1 221#define DISCONNECT_LONG 2 222 223/* 224 * These are "special" values for the tag parameter passed to NCR5380_select. 225 */ 226 227#define TAG_NEXT -1 /* Use next free tag */ 228#define TAG_NONE -2 /* 229 * Establish I_T_L nexus instead of I_T_L_Q 230 * even on SCSI-II devices. 231 */ 232 233/* 234 * These are "special" values for the irq and dma_channel fields of the 235 * Scsi_Host structure 236 */ 237 238#define SCSI_IRQ_NONE 255 239#define DMA_NONE 255 240#define IRQ_AUTO 254 241#define DMA_AUTO 254 242#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */ 243 244#define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */ 245#define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */ 246#define FLAG_NCR53C400 4 /* NCR53c400 */ 247#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */ 248#define FLAG_DTC3181E 16 /* DTC3181E */ 249 250#ifndef ASM 251struct NCR5380_hostdata { 252 NCR5380_implementation_fields; /* implementation specific */ 253 struct Scsi_Host *host; /* Host backpointer */ 254 unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */ 255 unsigned char targets_present; /* targets we have connected 256 to, so we can call a select 257 failure a retryable condition */ 258 volatile unsigned char busy[8]; /* index = target, bit = lun */ 259#if defined(REAL_DMA) || defined(REAL_DMA_POLL) 260 volatile int dma_len; /* requested length of DMA */ 261#endif 262 volatile unsigned char last_message; /* last message OUT */ 263 volatile Scsi_Cmnd *connected; /* currently connected command */ 264 volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */ 265 volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */ 266 volatile int restart_select; /* we have disconnected, 267 used to restart 268 NCR5380_select() */ 269 volatile unsigned aborted:1; /* flag, says aborted */ 270 int flags; 271 unsigned long time_expires; /* in jiffies, set prior to sleeping */ 272 int select_time; /* timer in select for target response */ 273 volatile Scsi_Cmnd *selecting; 274 struct delayed_work coroutine; /* our co-routine */ 275#ifdef NCR5380_STATS 276 unsigned timebase; /* Base for time calcs */ 277 long time_read[8]; /* time to do reads */ 278 long time_write[8]; /* time to do writes */ 279 unsigned long bytes_read[8]; /* bytes read */ 280 unsigned long bytes_write[8]; /* bytes written */ 281 unsigned pendingr; 282 unsigned pendingw; 283#endif 284#ifdef AUTOSENSE 285 struct scsi_eh_save ses; 286#endif 287}; 288 289#ifdef __KERNEL__ 290 291#define dprintk(a,b) do {} while(0) 292#define NCR5380_dprint(a,b) do {} while(0) 293#define NCR5380_dprint_phase(a,b) do {} while(0) 294 295#if defined(AUTOPROBE_IRQ) 296static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible); 297#endif 298static int NCR5380_init(struct Scsi_Host *instance, int flags); 299static void NCR5380_exit(struct Scsi_Host *instance); 300static void NCR5380_information_transfer(struct Scsi_Host *instance); 301#ifndef DONT_USE_INTR 302static irqreturn_t NCR5380_intr(int irq, void *dev_id); 303#endif 304static void NCR5380_main(struct work_struct *work); 305static void __maybe_unused NCR5380_print_options(struct Scsi_Host *instance); 306#ifdef NDEBUG 307static void NCR5380_print_phase(struct Scsi_Host *instance); 308static void NCR5380_print(struct Scsi_Host *instance); 309#endif 310static int NCR5380_abort(Scsi_Cmnd * cmd); 311static int NCR5380_bus_reset(Scsi_Cmnd * cmd); 312static int NCR5380_queue_command(Scsi_Cmnd * cmd, void (*done) (Scsi_Cmnd *)); 313static int __maybe_unused NCR5380_proc_info(struct Scsi_Host *instance, 314 char *buffer, char **start, off_t offset, int length, int inout); 315 316static void NCR5380_reselect(struct Scsi_Host *instance); 317static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd * cmd, int tag); 318#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL) 319static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data); 320#endif 321static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data); 322 323#if (defined(REAL_DMA) || defined(REAL_DMA_POLL)) 324 325#if defined(i386) || defined(__alpha__) 326 327/** 328 * NCR5380_pc_dma_setup - setup ISA DMA 329 * @instance: adapter to set up 330 * @ptr: block to transfer (virtual address) 331 * @count: number of bytes to transfer 332 * @mode: DMA controller mode to use 333 * 334 * Program the DMA controller ready to perform an ISA DMA transfer 335 * on this chip. 336 * 337 * Locks: takes and releases the ISA DMA lock. 338 */ 339 340static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode) 341{ 342 unsigned limit; 343 unsigned long bus_addr = virt_to_bus(ptr); 344 unsigned long flags; 345 346 if (instance->dma_channel <= 3) { 347 if (count > 65536) 348 count = 65536; 349 limit = 65536 - (bus_addr & 0xFFFF); 350 } else { 351 if (count > 65536 * 2) 352 count = 65536 * 2; 353 limit = 65536 * 2 - (bus_addr & 0x1FFFF); 354 } 355 356 if (count > limit) 357 count = limit; 358 359 if ((count & 1) || (bus_addr & 1)) 360 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no); 361 362 flags=claim_dma_lock(); 363 disable_dma(instance->dma_channel); 364 clear_dma_ff(instance->dma_channel); 365 set_dma_addr(instance->dma_channel, bus_addr); 366 set_dma_count(instance->dma_channel, count); 367 set_dma_mode(instance->dma_channel, mode); 368 enable_dma(instance->dma_channel); 369 release_dma_lock(flags); 370 371 return count; 372} 373 374/** 375 * NCR5380_pc_dma_write_setup - setup ISA DMA write 376 * @instance: adapter to set up 377 * @ptr: block to transfer (virtual address) 378 * @count: number of bytes to transfer 379 * 380 * Program the DMA controller ready to perform an ISA DMA write to the 381 * SCSI controller. 382 * 383 * Locks: called routines take and release the ISA DMA lock. 384 */ 385 386static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count) 387{ 388 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE); 389} 390 391/** 392 * NCR5380_pc_dma_read_setup - setup ISA DMA read 393 * @instance: adapter to set up 394 * @ptr: block to transfer (virtual address) 395 * @count: number of bytes to transfer 396 * 397 * Program the DMA controller ready to perform an ISA DMA read from the 398 * SCSI controller. 399 * 400 * Locks: called routines take and release the ISA DMA lock. 401 */ 402 403static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count) 404{ 405 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ); 406} 407 408/** 409 * NCR5380_pc_dma_residual - return bytes left 410 * @instance: adapter 411 * 412 * Reports the number of bytes left over after the DMA was terminated. 413 * 414 * Locks: takes and releases the ISA DMA lock. 415 */ 416 417static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance) 418{ 419 unsigned long flags; 420 int tmp; 421 422 flags = claim_dma_lock(); 423 clear_dma_ff(instance->dma_channel); 424 tmp = get_dma_residue(instance->dma_channel); 425 release_dma_lock(flags); 426 427 return tmp; 428} 429#endif /* defined(i386) || defined(__alpha__) */ 430#endif /* defined(REAL_DMA) */ 431#endif /* __KERNEL__ */ 432#endif /* ndef ASM */ 433#endif /* NCR5380_H */ 434