/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/ppc/ |
H A D | idecode_expression.h | 270 #define CR_SET(REG, VAL) MBLIT32(CR, REG*4, REG*4+3, VAL) 344 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) 347 #define FPSCR_SET_FPCC(VAL) MBLIT32(FPSCR, fpscr_fpcc_bit, fpscr_fpcc_bit+3, VAL)
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H A D | hw_phb.c | 413 MBLIT32(address->cells[0], 6, 7, val); 432 MBLIT32(address->cells[0], 8, 15, val); 449 MBLIT32(address->cells[0], 16, 20, val); 465 MBLIT32(address->cells[0], 21, 23, val); 481 MBLIT32(address->cells[0], 24, 31, val);
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H A D | bits.h | 258 #define MBLIT32(V, LO, HI, VAL) \ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/ppc/ |
H A D | idecode_expression.h | 270 #define CR_SET(REG, VAL) MBLIT32(CR, REG*4, REG*4+3, VAL) 344 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) 347 #define FPSCR_SET_FPCC(VAL) MBLIT32(FPSCR, fpscr_fpcc_bit, fpscr_fpcc_bit+3, VAL)
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H A D | hw_phb.c | 413 MBLIT32(address->cells[0], 6, 7, val); 432 MBLIT32(address->cells[0], 8, 15, val); 449 MBLIT32(address->cells[0], 16, 20, val); 465 MBLIT32(address->cells[0], 21, 23, val); 481 MBLIT32(address->cells[0], 24, 31, val);
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H A D | bits.h | 258 #define MBLIT32(V, LO, HI, VAL) \ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/ppc/ |
H A D | idecode_expression.h | 270 #define CR_SET(REG, VAL) MBLIT32(CR, REG*4, REG*4+3, VAL) 344 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) 347 #define FPSCR_SET_FPCC(VAL) MBLIT32(FPSCR, fpscr_fpcc_bit, fpscr_fpcc_bit+3, VAL)
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H A D | hw_phb.c | 413 MBLIT32(address->cells[0], 6, 7, val); 432 MBLIT32(address->cells[0], 8, 15, val); 449 MBLIT32(address->cells[0], 16, 20, val); 465 MBLIT32(address->cells[0], 21, 23, val); 481 MBLIT32(address->cells[0], 24, 31, val);
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H A D | bits.h | 258 #define MBLIT32(V, LO, HI, VAL) \ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/mips/ |
H A D | dv-tx3904tmr.c | 462 MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte); 470 MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/mips/ |
H A D | dv-tx3904tmr.c | 462 MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte); 470 MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/mips/ |
H A D | dv-tx3904tmr.c | 462 MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte); 470 MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/common/ |
H A D | sim-bits.h | 543 #define MBLIT32(V, LO, HI, VAL) \ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/common/ |
H A D | sim-bits.h | 543 #define MBLIT32(V, LO, HI, VAL) \ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/common/ |
H A D | sim-bits.h | 543 #define MBLIT32(V, LO, HI, VAL) \ macro
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