Searched refs:Imm8 (Results 1 - 15 of 15) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/
H A Di386-opc.h141 #define Imm8 0x10 /* 8 bit immediate */ macro
187 #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
188 #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
H A Di386-tbl.h39 { Imm8|Imm16|Imm32|Imm32S,
43 { Imm8|Imm16|Imm32|Imm32S,
255 { Imm8,
263 { Imm8 } },
270 Imm8 } },
277 { Imm8 } },
357 { Imm8|Imm16|Imm32|Imm32S,
361 { Imm8|Imm16|Imm32|Imm32S,
379 { Imm8|Imm16|Imm32|Imm32S,
383 { Imm8|Imm1
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/
H A Di386-opc.h141 #define Imm8 0x10 /* 8 bit immediate */ macro
187 #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
188 #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
H A Di386-tbl.h39 { Imm8|Imm16|Imm32|Imm32S,
43 { Imm8|Imm16|Imm32|Imm32S,
255 { Imm8,
263 { Imm8 } },
270 Imm8 } },
277 { Imm8 } },
357 { Imm8|Imm16|Imm32|Imm32S,
361 { Imm8|Imm16|Imm32|Imm32S,
379 { Imm8|Imm16|Imm32|Imm32S,
383 { Imm8|Imm1
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/
H A Di386-opc.h141 #define Imm8 0x10 /* 8 bit immediate */ macro
187 #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
188 #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
H A Di386-tbl.h39 { Imm8|Imm16|Imm32|Imm32S,
43 { Imm8|Imm16|Imm32|Imm32S,
255 { Imm8,
263 { Imm8 } },
270 Imm8 } },
277 { Imm8 } },
357 { Imm8|Imm16|Imm32|Imm32S,
361 { Imm8|Imm16|Imm32|Imm32S,
379 { Imm8|Imm16|Imm32|Imm32S,
383 { Imm8|Imm1
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/testsuite/sim/h8300/
H A Dmovw.s179 mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands.
211 mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands.
243 mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands
275 mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands
307 mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand
H A Dmovb.s154 mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands.
186 mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands.
218 mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands
250 mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands
282 mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
H A Dmovl.s142 mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands.
174 mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands.
206 mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands
238 mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands
270 mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/testsuite/sim/h8300/
H A Dmovw.s179 mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands.
211 mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands.
243 mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands
275 mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands
307 mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand
H A Dmovb.s154 mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands.
186 mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands.
218 mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands
250 mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands
282 mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
H A Dmovl.s142 mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands.
174 mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands.
206 mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands
238 mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands
270 mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/testsuite/sim/h8300/
H A Dmovw.s179 mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands.
211 mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands.
243 mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands
275 mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands
307 mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand
H A Dmovb.s154 mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands.
186 mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands.
218 mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands
250 mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands
282 mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
H A Dmovl.s142 mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands.
174 mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands.
206 mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands
238 mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands
270 mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand

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