1/* This file is automatically generated by i386-gen.  Do not edit!  */
2/* Copyright 2007  Free Software Foundation, Inc.
3
4   This file is part of the GNU opcodes library.
5
6   This library is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3, or (at your option)
9   any later version.
10
11   It is distributed in the hope that it will be useful, but WITHOUT
12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14   License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with this program; if not, write to the Free Software
18   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19   MA 02110-1301, USA.  */
20
21/* i386 opcode table.  */
22
23const template i386_optab[] =
24{
25  { "mov", 2, 0xa0, None, Cpu64,
26    D|W|No_sSuf|No_xSuf,
27    { Disp64,
28      Acc } },
29  { "mov", 2, 0xa0, None, CpuNo64,
30    D|W|No_sSuf|No_qSuf|No_xSuf,
31    { Disp16|Disp32,
32      Acc } },
33  { "mov", 2, 0x88, None, 0,
34    D|W|Modrm|No_sSuf|No_xSuf,
35    { Reg8|Reg16|Reg32|Reg64,
36      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
37  { "mov", 2, 0xb0, None, 0,
38    W|ShortForm|No_sSuf|No_qSuf|No_xSuf,
39    { Imm8|Imm16|Imm32|Imm32S,
40      Reg8|Reg16|Reg32 } },
41  { "mov", 2, 0xc6, 0x0, 0,
42    W|Modrm|No_sSuf|No_xSuf,
43    { Imm8|Imm16|Imm32|Imm32S,
44      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
45  { "mov", 2, 0xb0, None, Cpu64,
46    W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
47    { Imm64,
48      Reg64 } },
49  { "mov", 2, 0x8c, None, 0,
50    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
51    { SReg2,
52      Reg16|Reg32|Reg64|RegMem } },
53  { "mov", 2, 0x8c, None, 0,
54    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
55    { SReg2,
56      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
57  { "mov", 2, 0x8c, None, Cpu386,
58    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
59    { SReg3,
60      Reg16|Reg32|Reg64|RegMem } },
61  { "mov", 2, 0x8c, None, Cpu386,
62    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
63    { SReg3,
64      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
65  { "mov", 2, 0x8e, None, 0,
66    Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
67    { Reg16|Reg32|Reg64,
68      SReg2 } },
69  { "mov", 2, 0x8e, None, 0,
70    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
71    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
72      SReg2 } },
73  { "mov", 2, 0x8e, None, Cpu386,
74    Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
75    { Reg16|Reg32|Reg64,
76      SReg3 } },
77  { "mov", 2, 0x8e, None, Cpu386,
78    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
79    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
80      SReg3 } },
81  { "mov", 2, 0xf20, None, Cpu386|CpuNo64,
82    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
83    { Control,
84      Reg32|RegMem } },
85  { "mov", 2, 0xf20, None, Cpu64,
86    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
87    { Control,
88      Reg64|RegMem } },
89  { "mov", 2, 0xf21, None, Cpu386|CpuNo64,
90    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
91    { Debug,
92      Reg32|RegMem } },
93  { "mov", 2, 0xf21, None, Cpu64,
94    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
95    { Debug,
96      Reg64|RegMem } },
97  { "mov", 2, 0xf24, None, Cpu386|CpuNo64,
98    D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
99    { Test,
100      Reg32|RegMem } },
101  { "movabs", 2, 0xa0, None, Cpu64,
102    D|W|No_sSuf|No_xSuf,
103    { Disp64,
104      Acc } },
105  { "movabs", 2, 0xb0, None, Cpu64,
106    W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
107    { Imm64,
108      Reg64 } },
109  { "movsbl", 2, 0xfbe, None, Cpu386,
110    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
111    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
112      Reg32 } },
113  { "movsbw", 2, 0xfbe, None, Cpu386,
114    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
115    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
116      Reg16 } },
117  { "movswl", 2, 0xfbf, None, Cpu386,
118    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
119    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
120      Reg32 } },
121  { "movsbq", 2, 0xfbe, None, Cpu64,
122    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
123    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
124      Reg64 } },
125  { "movswq", 2, 0xfbf, None, Cpu64,
126    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
127    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
128      Reg64 } },
129  { "movslq", 2, 0x63, None, Cpu64,
130    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
131    { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
132      Reg64 } },
133  { "movsx", 2, 0xfbe, None, Cpu386,
134    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
135    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
136      Reg16|Reg32|Reg64 } },
137  { "movsx", 2, 0xfbf, None, Cpu386,
138    Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
139    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
140      Reg32|Reg64 } },
141  { "movsx", 2, 0x63, None, Cpu64,
142    Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
143    { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
144      Reg64 } },
145  { "movzb", 2, 0xfb6, None, Cpu386,
146    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
147    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
148      Reg16|Reg32|Reg64 } },
149  { "movzbl", 2, 0xfb6, None, Cpu386,
150    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
151    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
152      Reg32 } },
153  { "movzbw", 2, 0xfb6, None, Cpu386,
154    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
155    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
156      Reg16 } },
157  { "movzwl", 2, 0xfb7, None, Cpu386,
158    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
159    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
160      Reg32 } },
161  { "movzbq", 2, 0xfb6, None, Cpu64,
162    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
163    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
164      Reg64 } },
165  { "movzwq", 2, 0xfb7, None, Cpu64,
166    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
167    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
168      Reg64 } },
169  { "movzx", 2, 0xfb6, None, Cpu386,
170    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
171    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
172      Reg16|Reg32|Reg64 } },
173  { "movzx", 2, 0xfb7, None, Cpu386,
174    Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
175    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
176      Reg32|Reg64 } },
177  { "push", 1, 0x50, None, CpuNo64,
178    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
179    { Reg16|Reg32|Reg64 } },
180  { "push", 1, 0xff, 0x6, CpuNo64,
181    Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
182    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
183  { "push", 1, 0x6a, None, Cpu186|CpuNo64,
184    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
185    { Imm8S } },
186  { "push", 1, 0x68, None, Cpu186|CpuNo64,
187    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
188    { Imm16|Imm32 } },
189  { "push", 1, 0x6, None, CpuNo64,
190    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
191    { SReg2 } },
192  { "push", 1, 0xfa0, None, Cpu386|CpuNo64,
193    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
194    { SReg3 } },
195  { "push", 1, 0x50, None, Cpu64,
196    ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
197    { Reg16|Reg64 } },
198  { "push", 1, 0xff, 0x6, Cpu64,
199    Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
200    { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
201  { "push", 1, 0x6a, None, Cpu64,
202    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
203    { Imm8S } },
204  { "push", 1, 0x68, None, Cpu64,
205    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
206    { Imm16|Imm32S } },
207  { "push", 1, 0xfa0, None, Cpu64,
208    ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
209    { SReg3 } },
210  { "pusha", 0, 0x60, None, Cpu186|CpuNo64,
211    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
212    { 0 } },
213  { "pop", 1, 0x58, None, CpuNo64,
214    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
215    { Reg16|Reg32|Reg64 } },
216  { "pop", 1, 0x8f, 0x0, CpuNo64,
217    Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
218    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
219  { "pop", 1, 0x7, None, CpuNo64,
220    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
221    { SReg2 } },
222  { "pop", 1, 0xfa1, None, Cpu386|CpuNo64,
223    ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
224    { SReg3 } },
225  { "pop", 1, 0x58, None, Cpu64,
226    ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
227    { Reg16|Reg64 } },
228  { "pop", 1, 0x8f, 0x0, Cpu64,
229    Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
230    { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
231  { "pop", 1, 0xfa1, None, Cpu64,
232    ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
233    { SReg3 } },
234  { "popa", 0, 0x61, None, Cpu186|CpuNo64,
235    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
236    { 0 } },
237  { "xchg", 2, 0x90, None, 0,
238    ShortForm|No_bSuf|No_sSuf|No_xSuf,
239    { Reg16|Reg32|Reg64,
240      Acc } },
241  { "xchg", 2, 0x90, None, 0,
242    ShortForm|No_bSuf|No_sSuf|No_xSuf,
243    { Acc,
244      Reg16|Reg32|Reg64 } },
245  { "xchg", 2, 0x86, None, 0,
246    W|Modrm|No_sSuf|No_xSuf,
247    { Reg8|Reg16|Reg32|Reg64,
248      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
249  { "xchg", 2, 0x86, None, 0,
250    W|Modrm|No_sSuf|No_xSuf,
251    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
252      Reg8|Reg16|Reg32|Reg64 } },
253  { "in", 2, 0xe4, None, 0,
254    W|No_sSuf|No_qSuf|No_xSuf,
255    { Imm8,
256      Acc } },
257  { "in", 2, 0xec, None, 0,
258    W|No_sSuf|No_qSuf|No_xSuf,
259    { InOutPortReg,
260      Acc } },
261  { "in", 1, 0xe4, None, 0,
262    W|No_sSuf|No_qSuf|No_xSuf,
263    { Imm8 } },
264  { "in", 1, 0xec, None, 0,
265    W|No_sSuf|No_qSuf|No_xSuf,
266    { InOutPortReg } },
267  { "out", 2, 0xe6, None, 0,
268    W|No_sSuf|No_qSuf|No_xSuf,
269    { Acc,
270      Imm8 } },
271  { "out", 2, 0xee, None, 0,
272    W|No_sSuf|No_qSuf|No_xSuf,
273    { Acc,
274      InOutPortReg } },
275  { "out", 1, 0xe6, None, 0,
276    W|No_sSuf|No_qSuf|No_xSuf,
277    { Imm8 } },
278  { "out", 1, 0xee, None, 0,
279    W|No_sSuf|No_qSuf|No_xSuf,
280    { InOutPortReg } },
281  { "lea", 2, 0x8d, None, 0,
282    Modrm|No_bSuf|No_sSuf|No_xSuf,
283    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
284      Reg16|Reg32|Reg64 } },
285  { "lds", 2, 0xc5, None, CpuNo64,
286    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
287    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
288      Reg16|Reg32|Reg64 } },
289  { "les", 2, 0xc4, None, CpuNo64,
290    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
291    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
292      Reg16|Reg32|Reg64 } },
293  { "lfs", 2, 0xfb4, None, Cpu386,
294    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
295    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
296      Reg16|Reg32|Reg64 } },
297  { "lgs", 2, 0xfb5, None, Cpu386,
298    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
299    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
300      Reg16|Reg32|Reg64 } },
301  { "lss", 2, 0xfb2, None, Cpu386,
302    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
303    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
304      Reg16|Reg32|Reg64 } },
305  { "clc", 0, 0xf8, None, 0,
306    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
307    { 0 } },
308  { "cld", 0, 0xfc, None, 0,
309    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
310    { 0 } },
311  { "cli", 0, 0xfa, None, 0,
312    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
313    { 0 } },
314  { "clts", 0, 0xf06, None, Cpu286,
315    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
316    { 0 } },
317  { "cmc", 0, 0xf5, None, 0,
318    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
319    { 0 } },
320  { "lahf", 0, 0x9f, None, 0,
321    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
322    { 0 } },
323  { "sahf", 0, 0x9e, None, 0,
324    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
325    { 0 } },
326  { "pushf", 0, 0x9c, None, CpuNo64,
327    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
328    { 0 } },
329  { "pushf", 0, 0x9c, None, Cpu64,
330    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
331    { 0 } },
332  { "popf", 0, 0x9d, None, CpuNo64,
333    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
334    { 0 } },
335  { "popf", 0, 0x9d, None, Cpu64,
336    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
337    { 0 } },
338  { "stc", 0, 0xf9, None, 0,
339    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
340    { 0 } },
341  { "std", 0, 0xfd, None, 0,
342    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
343    { 0 } },
344  { "sti", 0, 0xfb, None, 0,
345    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
346    { 0 } },
347  { "add", 2, 0x0, None, 0,
348    D|W|Modrm|No_sSuf|No_xSuf,
349    { Reg8|Reg16|Reg32|Reg64,
350      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
351  { "add", 2, 0x83, 0x0, 0,
352    Modrm|No_bSuf|No_sSuf|No_xSuf,
353    { Imm8S,
354      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
355  { "add", 2, 0x4, None, 0,
356    W|No_sSuf|No_xSuf,
357    { Imm8|Imm16|Imm32|Imm32S,
358      Acc } },
359  { "add", 2, 0x80, 0x0, 0,
360    W|Modrm|No_sSuf|No_xSuf,
361    { Imm8|Imm16|Imm32|Imm32S,
362      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
363  { "inc", 1, 0x40, None, CpuNo64,
364    ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
365    { Reg16|Reg32|Reg64 } },
366  { "inc", 1, 0xfe, 0x0, 0,
367    W|Modrm|No_sSuf|No_xSuf,
368    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
369  { "sub", 2, 0x28, None, 0,
370    D|W|Modrm|No_sSuf|No_xSuf,
371    { Reg8|Reg16|Reg32|Reg64,
372      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
373  { "sub", 2, 0x83, 0x5, 0,
374    Modrm|No_bSuf|No_sSuf|No_xSuf,
375    { Imm8S,
376      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
377  { "sub", 2, 0x2c, None, 0,
378    W|No_sSuf|No_xSuf,
379    { Imm8|Imm16|Imm32|Imm32S,
380      Acc } },
381  { "sub", 2, 0x80, 0x5, 0,
382    W|Modrm|No_sSuf|No_xSuf,
383    { Imm8|Imm16|Imm32|Imm32S,
384      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
385  { "dec", 1, 0x48, None, CpuNo64,
386    ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
387    { Reg16|Reg32|Reg64 } },
388  { "dec", 1, 0xfe, 0x1, 0,
389    W|Modrm|No_sSuf|No_xSuf,
390    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
391  { "sbb", 2, 0x18, None, 0,
392    D|W|Modrm|No_sSuf|No_xSuf,
393    { Reg8|Reg16|Reg32|Reg64,
394      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
395  { "sbb", 2, 0x83, 0x3, 0,
396    Modrm|No_bSuf|No_sSuf|No_xSuf,
397    { Imm8S,
398      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
399  { "sbb", 2, 0x1c, None, 0,
400    W|No_sSuf|No_xSuf,
401    { Imm8|Imm16|Imm32|Imm32S,
402      Acc } },
403  { "sbb", 2, 0x80, 0x3, 0,
404    W|Modrm|No_sSuf|No_xSuf,
405    { Imm8|Imm16|Imm32|Imm32S,
406      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
407  { "cmp", 2, 0x38, None, 0,
408    D|W|Modrm|No_sSuf|No_xSuf,
409    { Reg8|Reg16|Reg32|Reg64,
410      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
411  { "cmp", 2, 0x83, 0x7, 0,
412    Modrm|No_bSuf|No_sSuf|No_xSuf,
413    { Imm8S,
414      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
415  { "cmp", 2, 0x3c, None, 0,
416    W|No_sSuf|No_xSuf,
417    { Imm8|Imm16|Imm32|Imm32S,
418      Acc } },
419  { "cmp", 2, 0x80, 0x7, 0,
420    W|Modrm|No_sSuf|No_xSuf,
421    { Imm8|Imm16|Imm32|Imm32S,
422      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
423  { "test", 2, 0x84, None, 0,
424    W|Modrm|No_sSuf|No_xSuf,
425    { Reg8|Reg16|Reg32|Reg64,
426      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
427  { "test", 2, 0x84, None, 0,
428    W|Modrm|No_sSuf|No_xSuf,
429    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
430      Reg8|Reg16|Reg32|Reg64 } },
431  { "test", 2, 0xa8, None, 0,
432    W|No_sSuf|No_xSuf,
433    { Imm8|Imm16|Imm32|Imm32S,
434      Acc } },
435  { "test", 2, 0xf6, 0x0, 0,
436    W|Modrm|No_sSuf|No_xSuf,
437    { Imm8|Imm16|Imm32|Imm32S,
438      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
439  { "and", 2, 0x20, None, 0,
440    D|W|Modrm|No_sSuf|No_xSuf,
441    { Reg8|Reg16|Reg32|Reg64,
442      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
443  { "and", 2, 0x83, 0x4, 0,
444    Modrm|No_bSuf|No_sSuf|No_xSuf,
445    { Imm8S,
446      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
447  { "and", 2, 0x24, None, 0,
448    W|No_sSuf|No_xSuf,
449    { Imm8|Imm16|Imm32|Imm32S,
450      Acc } },
451  { "and", 2, 0x80, 0x4, 0,
452    W|Modrm|No_sSuf|No_xSuf,
453    { Imm8|Imm16|Imm32|Imm32S,
454      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
455  { "or", 2, 0x8, None, 0,
456    D|W|Modrm|No_sSuf|No_xSuf,
457    { Reg8|Reg16|Reg32|Reg64,
458      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
459  { "or", 2, 0x83, 0x1, 0,
460    Modrm|No_bSuf|No_sSuf|No_xSuf,
461    { Imm8S,
462      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
463  { "or", 2, 0xc, None, 0,
464    W|No_sSuf|No_xSuf,
465    { Imm8|Imm16|Imm32|Imm32S,
466      Acc } },
467  { "or", 2, 0x80, 0x1, 0,
468    W|Modrm|No_sSuf|No_xSuf,
469    { Imm8|Imm16|Imm32|Imm32S,
470      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
471  { "xor", 2, 0x30, None, 0,
472    D|W|Modrm|No_sSuf|No_xSuf,
473    { Reg8|Reg16|Reg32|Reg64,
474      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
475  { "xor", 2, 0x83, 0x6, 0,
476    Modrm|No_bSuf|No_sSuf|No_xSuf,
477    { Imm8S,
478      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
479  { "xor", 2, 0x34, None, 0,
480    W|No_sSuf|No_xSuf,
481    { Imm8|Imm16|Imm32|Imm32S,
482      Acc } },
483  { "xor", 2, 0x80, 0x6, 0,
484    W|Modrm|No_sSuf|No_xSuf,
485    { Imm8|Imm16|Imm32|Imm32S,
486      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
487  { "clr", 1, 0x30, None, 0,
488    W|Modrm|No_sSuf|No_xSuf|RegKludge,
489    { Reg8|Reg16|Reg32|Reg64 } },
490  { "adc", 2, 0x10, None, 0,
491    D|W|Modrm|No_sSuf|No_xSuf,
492    { Reg8|Reg16|Reg32|Reg64,
493      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
494  { "adc", 2, 0x83, 0x2, 0,
495    Modrm|No_bSuf|No_sSuf|No_xSuf,
496    { Imm8S,
497      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
498  { "adc", 2, 0x14, None, 0,
499    W|No_sSuf|No_xSuf,
500    { Imm8|Imm16|Imm32|Imm32S,
501      Acc } },
502  { "adc", 2, 0x80, 0x2, 0,
503    W|Modrm|No_sSuf|No_xSuf,
504    { Imm8|Imm16|Imm32|Imm32S,
505      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
506  { "neg", 1, 0xf6, 0x3, 0,
507    W|Modrm|No_sSuf|No_xSuf,
508    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
509  { "not", 1, 0xf6, 0x2, 0,
510    W|Modrm|No_sSuf|No_xSuf,
511    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
512  { "aaa", 0, 0x37, None, CpuNo64,
513    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
514    { 0 } },
515  { "aas", 0, 0x3f, None, CpuNo64,
516    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
517    { 0 } },
518  { "daa", 0, 0x27, None, CpuNo64,
519    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
520    { 0 } },
521  { "das", 0, 0x2f, None, CpuNo64,
522    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
523    { 0 } },
524  { "aad", 0, 0xd50a, None, CpuNo64,
525    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
526    { 0 } },
527  { "aad", 1, 0xd5, None, CpuNo64,
528    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
529    { Imm8 } },
530  { "aam", 0, 0xd40a, None, CpuNo64,
531    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
532    { 0 } },
533  { "aam", 1, 0xd4, None, CpuNo64,
534    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
535    { Imm8 } },
536  { "cbw", 0, 0x98, None, 0,
537    Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
538    { 0 } },
539  { "cdqe", 0, 0x98, None, Cpu64,
540    Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
541    { 0 } },
542  { "cwde", 0, 0x98, None, 0,
543    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
544    { 0 } },
545  { "cwd", 0, 0x99, None, 0,
546    Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
547    { 0 } },
548  { "cdq", 0, 0x99, None, 0,
549    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
550    { 0 } },
551  { "cqo", 0, 0x99, None, Cpu64,
552    Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
553    { 0 } },
554  { "cbtw", 0, 0x98, None, 0,
555    Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
556    { 0 } },
557  { "cltq", 0, 0x98, None, Cpu64,
558    Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
559    { 0 } },
560  { "cwtl", 0, 0x98, None, 0,
561    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
562    { 0 } },
563  { "cwtd", 0, 0x99, None, 0,
564    Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
565    { 0 } },
566  { "cltd", 0, 0x99, None, 0,
567    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
568    { 0 } },
569  { "cqto", 0, 0x99, None, Cpu64,
570    Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
571    { 0 } },
572  { "mul", 1, 0xf6, 0x4, 0,
573    W|Modrm|No_sSuf|No_xSuf,
574    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
575  { "imul", 1, 0xf6, 0x5, 0,
576    W|Modrm|No_sSuf|No_xSuf,
577    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
578  { "imul", 2, 0xfaf, None, Cpu386,
579    Modrm|No_bSuf|No_sSuf|No_xSuf,
580    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
581      Reg16|Reg32|Reg64 } },
582  { "imul", 3, 0x6b, None, Cpu186,
583    Modrm|No_bSuf|No_sSuf|No_xSuf,
584    { Imm8S,
585      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
586      Reg16|Reg32|Reg64 } },
587  { "imul", 3, 0x69, None, Cpu186,
588    Modrm|No_bSuf|No_sSuf|No_xSuf,
589    { Imm16|Imm32|Imm32S,
590      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
591      Reg16|Reg32|Reg64 } },
592  { "imul", 2, 0x6b, None, Cpu186,
593    Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge,
594    { Imm8S,
595      Reg16|Reg32|Reg64 } },
596  { "imul", 2, 0x69, None, Cpu186,
597    Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge,
598    { Imm16|Imm32|Imm32S,
599      Reg16|Reg32|Reg64 } },
600  { "div", 1, 0xf6, 0x6, 0,
601    W|Modrm|No_sSuf|No_xSuf,
602    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
603  { "div", 2, 0xf6, 0x6, 0,
604    W|Modrm|No_sSuf|No_xSuf,
605    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
606      Acc } },
607  { "idiv", 1, 0xf6, 0x7, 0,
608    W|Modrm|No_sSuf|No_xSuf,
609    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
610  { "idiv", 2, 0xf6, 0x7, 0,
611    W|Modrm|No_sSuf|No_xSuf,
612    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
613      Acc } },
614  { "rol", 2, 0xd0, 0x0, 0,
615    W|Modrm|No_sSuf|No_xSuf,
616    { Imm1,
617      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
618  { "rol", 2, 0xc0, 0x0, Cpu186,
619    W|Modrm|No_sSuf|No_xSuf,
620    { Imm8,
621      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
622  { "rol", 2, 0xd2, 0x0, 0,
623    W|Modrm|No_sSuf|No_xSuf,
624    { ShiftCount,
625      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
626  { "rol", 1, 0xd0, 0x0, 0,
627    W|Modrm|No_sSuf|No_xSuf,
628    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
629  { "ror", 2, 0xd0, 0x1, 0,
630    W|Modrm|No_sSuf|No_xSuf,
631    { Imm1,
632      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
633  { "ror", 2, 0xc0, 0x1, Cpu186,
634    W|Modrm|No_sSuf|No_xSuf,
635    { Imm8,
636      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
637  { "ror", 2, 0xd2, 0x1, 0,
638    W|Modrm|No_sSuf|No_xSuf,
639    { ShiftCount,
640      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
641  { "ror", 1, 0xd0, 0x1, 0,
642    W|Modrm|No_sSuf|No_xSuf,
643    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
644  { "rcl", 2, 0xd0, 0x2, 0,
645    W|Modrm|No_sSuf|No_xSuf,
646    { Imm1,
647      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
648  { "rcl", 2, 0xc0, 0x2, Cpu186,
649    W|Modrm|No_sSuf|No_xSuf,
650    { Imm8,
651      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
652  { "rcl", 2, 0xd2, 0x2, 0,
653    W|Modrm|No_sSuf|No_xSuf,
654    { ShiftCount,
655      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
656  { "rcl", 1, 0xd0, 0x2, 0,
657    W|Modrm|No_sSuf|No_xSuf,
658    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
659  { "rcr", 2, 0xd0, 0x3, 0,
660    W|Modrm|No_sSuf|No_xSuf,
661    { Imm1,
662      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
663  { "rcr", 2, 0xc0, 0x3, Cpu186,
664    W|Modrm|No_sSuf|No_xSuf,
665    { Imm8,
666      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
667  { "rcr", 2, 0xd2, 0x3, 0,
668    W|Modrm|No_sSuf|No_xSuf,
669    { ShiftCount,
670      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
671  { "rcr", 1, 0xd0, 0x3, 0,
672    W|Modrm|No_sSuf|No_xSuf,
673    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
674  { "sal", 2, 0xd0, 0x4, 0,
675    W|Modrm|No_sSuf|No_xSuf,
676    { Imm1,
677      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
678  { "sal", 2, 0xc0, 0x4, Cpu186,
679    W|Modrm|No_sSuf|No_xSuf,
680    { Imm8,
681      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
682  { "sal", 2, 0xd2, 0x4, 0,
683    W|Modrm|No_sSuf|No_xSuf,
684    { ShiftCount,
685      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
686  { "sal", 1, 0xd0, 0x4, 0,
687    W|Modrm|No_sSuf|No_xSuf,
688    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
689  { "shl", 2, 0xd0, 0x4, 0,
690    W|Modrm|No_sSuf|No_xSuf,
691    { Imm1,
692      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
693  { "shl", 2, 0xc0, 0x4, Cpu186,
694    W|Modrm|No_sSuf|No_xSuf,
695    { Imm8,
696      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
697  { "shl", 2, 0xd2, 0x4, 0,
698    W|Modrm|No_sSuf|No_xSuf,
699    { ShiftCount,
700      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
701  { "shl", 1, 0xd0, 0x4, 0,
702    W|Modrm|No_sSuf|No_xSuf,
703    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
704  { "shr", 2, 0xd0, 0x5, 0,
705    W|Modrm|No_sSuf|No_xSuf,
706    { Imm1,
707      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
708  { "shr", 2, 0xc0, 0x5, Cpu186,
709    W|Modrm|No_sSuf|No_xSuf,
710    { Imm8,
711      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
712  { "shr", 2, 0xd2, 0x5, 0,
713    W|Modrm|No_sSuf|No_xSuf,
714    { ShiftCount,
715      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
716  { "shr", 1, 0xd0, 0x5, 0,
717    W|Modrm|No_sSuf|No_xSuf,
718    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
719  { "sar", 2, 0xd0, 0x7, 0,
720    W|Modrm|No_sSuf|No_xSuf,
721    { Imm1,
722      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
723  { "sar", 2, 0xc0, 0x7, Cpu186,
724    W|Modrm|No_sSuf|No_xSuf,
725    { Imm8,
726      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
727  { "sar", 2, 0xd2, 0x7, 0,
728    W|Modrm|No_sSuf|No_xSuf,
729    { ShiftCount,
730      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
731  { "sar", 1, 0xd0, 0x7, 0,
732    W|Modrm|No_sSuf|No_xSuf,
733    { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
734  { "shld", 3, 0xfa4, None, Cpu386,
735    Modrm|No_bSuf|No_sSuf|No_xSuf,
736    { Imm8,
737      Reg16|Reg32|Reg64,
738      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
739  { "shld", 3, 0xfa5, None, Cpu386,
740    Modrm|No_bSuf|No_sSuf|No_xSuf,
741    { ShiftCount,
742      Reg16|Reg32|Reg64,
743      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
744  { "shld", 2, 0xfa5, None, Cpu386,
745    Modrm|No_bSuf|No_sSuf|No_xSuf,
746    { Reg16|Reg32|Reg64,
747      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
748  { "shrd", 3, 0xfac, None, Cpu386,
749    Modrm|No_bSuf|No_sSuf|No_xSuf,
750    { Imm8,
751      Reg16|Reg32|Reg64,
752      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
753  { "shrd", 3, 0xfad, None, Cpu386,
754    Modrm|No_bSuf|No_sSuf|No_xSuf,
755    { ShiftCount,
756      Reg16|Reg32|Reg64,
757      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
758  { "shrd", 2, 0xfad, None, Cpu386,
759    Modrm|No_bSuf|No_sSuf|No_xSuf,
760    { Reg16|Reg32|Reg64,
761      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
762  { "call", 1, 0xe8, None, CpuNo64,
763    JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
764    { Disp16|Disp32 } },
765  { "call", 1, 0xe8, None, Cpu64,
766    JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
767    { Disp16|Disp32 } },
768  { "call", 1, 0xff, 0x2, CpuNo64,
769    Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
770    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
771  { "call", 1, 0xff, 0x2, Cpu64,
772    Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
773    { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
774  { "call", 2, 0x9a, None, CpuNo64,
775    JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
776    { Imm16,
777      Imm16|Imm32 } },
778  { "call", 1, 0xff, 0x3, 0,
779    Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
780    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
781  { "lcall", 2, 0x9a, None, CpuNo64,
782    JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
783    { Imm16,
784      Imm16|Imm32 } },
785  { "lcall", 1, 0xff, 0x3, 0,
786    Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
787    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
788  { "jmp", 1, 0xeb, None, 0,
789    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
790    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
791  { "jmp", 1, 0xff, 0x4, CpuNo64,
792    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
793    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
794  { "jmp", 1, 0xff, 0x4, Cpu64,
795    Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
796    { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
797  { "jmp", 2, 0xea, None, CpuNo64,
798    JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
799    { Imm16,
800      Imm16|Imm32 } },
801  { "jmp", 1, 0xff, 0x5, 0,
802    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
803    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
804  { "ljmp", 2, 0xea, None, CpuNo64,
805    JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
806    { Imm16,
807      Imm16|Imm32 } },
808  { "ljmp", 1, 0xff, 0x5, 0,
809    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
810    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
811  { "ret", 0, 0xc3, None, CpuNo64,
812    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
813    { 0 } },
814  { "ret", 1, 0xc2, None, CpuNo64,
815    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
816    { Imm16 } },
817  { "ret", 0, 0xc3, None, Cpu64,
818    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
819    { 0 } },
820  { "ret", 1, 0xc2, None, Cpu64,
821    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
822    { Imm16 } },
823  { "lret", 0, 0xcb, None, 0,
824    DefaultSize|No_bSuf|No_sSuf|No_xSuf,
825    { 0 } },
826  { "lret", 1, 0xca, None, 0,
827    DefaultSize|No_bSuf|No_sSuf|No_xSuf,
828    { Imm16 } },
829  { "enter", 2, 0xc8, None, Cpu186|CpuNo64,
830    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
831    { Imm16,
832      Imm8 } },
833  { "enter", 2, 0xc8, None, Cpu64,
834    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
835    { Imm16,
836      Imm8 } },
837  { "leave", 0, 0xc9, None, Cpu186|CpuNo64,
838    DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
839    { 0 } },
840  { "leave", 0, 0xc9, None, Cpu64,
841    DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
842    { 0 } },
843  { "jo", 1, 0x70, None, 0,
844    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
845    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
846  { "jno", 1, 0x71, None, 0,
847    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
848    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
849  { "jb", 1, 0x72, None, 0,
850    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
851    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
852  { "jc", 1, 0x72, None, 0,
853    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
854    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
855  { "jnae", 1, 0x72, None, 0,
856    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
857    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
858  { "jnb", 1, 0x73, None, 0,
859    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
860    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
861  { "jnc", 1, 0x73, None, 0,
862    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
863    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
864  { "jae", 1, 0x73, None, 0,
865    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
866    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
867  { "je", 1, 0x74, None, 0,
868    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
869    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
870  { "jz", 1, 0x74, None, 0,
871    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
872    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
873  { "jne", 1, 0x75, None, 0,
874    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
875    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
876  { "jnz", 1, 0x75, None, 0,
877    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
878    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
879  { "jbe", 1, 0x76, None, 0,
880    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
881    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
882  { "jna", 1, 0x76, None, 0,
883    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
884    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
885  { "jnbe", 1, 0x77, None, 0,
886    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
887    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
888  { "ja", 1, 0x77, None, 0,
889    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
890    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
891  { "js", 1, 0x78, None, 0,
892    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
893    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
894  { "jns", 1, 0x79, None, 0,
895    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
896    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
897  { "jp", 1, 0x7a, None, 0,
898    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
899    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
900  { "jpe", 1, 0x7a, None, 0,
901    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
902    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
903  { "jnp", 1, 0x7b, None, 0,
904    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
905    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
906  { "jpo", 1, 0x7b, None, 0,
907    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
908    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
909  { "jl", 1, 0x7c, None, 0,
910    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
911    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
912  { "jnge", 1, 0x7c, None, 0,
913    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
914    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
915  { "jnl", 1, 0x7d, None, 0,
916    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
917    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
918  { "jge", 1, 0x7d, None, 0,
919    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
920    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
921  { "jle", 1, 0x7e, None, 0,
922    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
923    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
924  { "jng", 1, 0x7e, None, 0,
925    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
926    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
927  { "jnle", 1, 0x7f, None, 0,
928    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
929    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
930  { "jg", 1, 0x7f, None, 0,
931    Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
932    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
933  { "jcxz", 1, 0xe3, None, CpuNo64,
934    JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
935    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
936  { "jecxz", 1, 0xe3, None, CpuNo64,
937    JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
938    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
939  { "jecxz", 1, 0x67e3, None, Cpu64,
940    JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
941    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
942  { "jrcxz", 1, 0xe3, None, Cpu64,
943    JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
944    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
945  { "loop", 1, 0xe2, None, CpuNo64,
946    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
947    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
948  { "loop", 1, 0xe2, None, Cpu64,
949    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
950    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
951  { "loopz", 1, 0xe1, None, CpuNo64,
952    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
953    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
954  { "loopz", 1, 0xe1, None, Cpu64,
955    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
956    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
957  { "loope", 1, 0xe1, None, CpuNo64,
958    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
959    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
960  { "loope", 1, 0xe1, None, Cpu64,
961    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
962    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
963  { "loopnz", 1, 0xe0, None, CpuNo64,
964    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
965    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
966  { "loopnz", 1, 0xe0, None, Cpu64,
967    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
968    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
969  { "loopne", 1, 0xe0, None, CpuNo64,
970    JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
971    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
972  { "loopne", 1, 0xe0, None, Cpu64,
973    JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
974    { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
975  { "seto", 1, 0xf90, 0x0, Cpu386,
976    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
977    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
978  { "setno", 1, 0xf91, 0x0, Cpu386,
979    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
980    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
981  { "setb", 1, 0xf92, 0x0, Cpu386,
982    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
983    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
984  { "setc", 1, 0xf92, 0x0, Cpu386,
985    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
986    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
987  { "setnae", 1, 0xf92, 0x0, Cpu386,
988    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
989    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
990  { "setnb", 1, 0xf93, 0x0, Cpu386,
991    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
992    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
993  { "setnc", 1, 0xf93, 0x0, Cpu386,
994    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
995    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
996  { "setae", 1, 0xf93, 0x0, Cpu386,
997    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
998    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
999  { "sete", 1, 0xf94, 0x0, Cpu386,
1000    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1001    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1002  { "setz", 1, 0xf94, 0x0, Cpu386,
1003    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1004    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1005  { "setne", 1, 0xf95, 0x0, Cpu386,
1006    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1007    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1008  { "setnz", 1, 0xf95, 0x0, Cpu386,
1009    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1010    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1011  { "setbe", 1, 0xf96, 0x0, Cpu386,
1012    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1013    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1014  { "setna", 1, 0xf96, 0x0, Cpu386,
1015    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1016    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1017  { "setnbe", 1, 0xf97, 0x0, Cpu386,
1018    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1019    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1020  { "seta", 1, 0xf97, 0x0, Cpu386,
1021    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1022    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1023  { "sets", 1, 0xf98, 0x0, Cpu386,
1024    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1025    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1026  { "setns", 1, 0xf99, 0x0, Cpu386,
1027    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1028    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1029  { "setp", 1, 0xf9a, 0x0, Cpu386,
1030    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1031    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1032  { "setpe", 1, 0xf9a, 0x0, Cpu386,
1033    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1034    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1035  { "setnp", 1, 0xf9b, 0x0, Cpu386,
1036    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1037    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1038  { "setpo", 1, 0xf9b, 0x0, Cpu386,
1039    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1040    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1041  { "setl", 1, 0xf9c, 0x0, Cpu386,
1042    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1043    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1044  { "setnge", 1, 0xf9c, 0x0, Cpu386,
1045    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1046    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1047  { "setnl", 1, 0xf9d, 0x0, Cpu386,
1048    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1049    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1050  { "setge", 1, 0xf9d, 0x0, Cpu386,
1051    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1052    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1053  { "setle", 1, 0xf9e, 0x0, Cpu386,
1054    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1055    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1056  { "setng", 1, 0xf9e, 0x0, Cpu386,
1057    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1058    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1059  { "setnle", 1, 0xf9f, 0x0, Cpu386,
1060    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1061    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1062  { "setg", 1, 0xf9f, 0x0, Cpu386,
1063    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1064    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1065  { "cmps", 0, 0xa6, None, 0,
1066    W|No_sSuf|No_xSuf|IsString,
1067    { 0 } },
1068  { "cmps", 2, 0xa6, None, 0,
1069    W|No_sSuf|No_xSuf|IsString,
1070    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1071      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1072  { "scmp", 0, 0xa6, None, 0,
1073    W|No_sSuf|No_xSuf|IsString,
1074    { 0 } },
1075  { "scmp", 2, 0xa6, None, 0,
1076    W|No_sSuf|No_xSuf|IsString,
1077    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1078      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1079  { "ins", 0, 0x6c, None, Cpu186,
1080    W|No_sSuf|No_qSuf|No_xSuf|IsString,
1081    { 0 } },
1082  { "ins", 2, 0x6c, None, Cpu186,
1083    W|No_sSuf|No_qSuf|No_xSuf|IsString,
1084    { InOutPortReg,
1085      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1086  { "outs", 0, 0x6e, None, Cpu186,
1087    W|No_sSuf|No_qSuf|No_xSuf|IsString,
1088    { 0 } },
1089  { "outs", 2, 0x6e, None, Cpu186,
1090    W|No_sSuf|No_qSuf|No_xSuf|IsString,
1091    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1092      InOutPortReg } },
1093  { "lods", 0, 0xac, None, 0,
1094    W|No_sSuf|No_xSuf|IsString,
1095    { 0 } },
1096  { "lods", 1, 0xac, None, 0,
1097    W|No_sSuf|No_xSuf|IsString,
1098    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1099  { "lods", 2, 0xac, None, 0,
1100    W|No_sSuf|No_xSuf|IsString,
1101    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1102      Acc } },
1103  { "slod", 0, 0xac, None, 0,
1104    W|No_sSuf|No_xSuf|IsString,
1105    { 0 } },
1106  { "slod", 1, 0xac, None, 0,
1107    W|No_sSuf|No_xSuf|IsString,
1108    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1109  { "slod", 2, 0xac, None, 0,
1110    W|No_sSuf|No_xSuf|IsString,
1111    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1112      Acc } },
1113  { "movs", 0, 0xa4, None, 0,
1114    W|No_sSuf|No_xSuf|IsString,
1115    { 0 } },
1116  { "movs", 2, 0xa4, None, 0,
1117    W|No_sSuf|No_xSuf|IsString,
1118    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1119      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1120  { "smov", 0, 0xa4, None, 0,
1121    W|No_sSuf|No_xSuf|IsString,
1122    { 0 } },
1123  { "smov", 2, 0xa4, None, 0,
1124    W|No_sSuf|No_xSuf|IsString,
1125    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1126      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1127  { "scas", 0, 0xae, None, 0,
1128    W|No_sSuf|No_xSuf|IsString,
1129    { 0 } },
1130  { "scas", 1, 0xae, None, 0,
1131    W|No_sSuf|No_xSuf|IsString,
1132    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1133  { "scas", 2, 0xae, None, 0,
1134    W|No_sSuf|No_xSuf|IsString,
1135    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1136      Acc } },
1137  { "ssca", 0, 0xae, None, 0,
1138    W|No_sSuf|No_xSuf|IsString,
1139    { 0 } },
1140  { "ssca", 1, 0xae, None, 0,
1141    W|No_sSuf|No_xSuf|IsString,
1142    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1143  { "ssca", 2, 0xae, None, 0,
1144    W|No_sSuf|No_xSuf|IsString,
1145    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1146      Acc } },
1147  { "stos", 0, 0xaa, None, 0,
1148    W|No_sSuf|No_xSuf|IsString,
1149    { 0 } },
1150  { "stos", 1, 0xaa, None, 0,
1151    W|No_sSuf|No_xSuf|IsString,
1152    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1153  { "stos", 2, 0xaa, None, 0,
1154    W|No_sSuf|No_xSuf|IsString,
1155    { Acc,
1156      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1157  { "ssto", 0, 0xaa, None, 0,
1158    W|No_sSuf|No_xSuf|IsString,
1159    { 0 } },
1160  { "ssto", 1, 0xaa, None, 0,
1161    W|No_sSuf|No_xSuf|IsString,
1162    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1163  { "ssto", 2, 0xaa, None, 0,
1164    W|No_sSuf|No_xSuf|IsString,
1165    { Acc,
1166      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1167  { "xlat", 0, 0xd7, None, 0,
1168    No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
1169    { 0 } },
1170  { "xlat", 1, 0xd7, None, 0,
1171    No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
1172    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1173  { "bsf", 2, 0xfbc, None, Cpu386,
1174    Modrm|No_bSuf|No_sSuf|No_xSuf,
1175    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1176      Reg16|Reg32|Reg64 } },
1177  { "bsr", 2, 0xfbd, None, Cpu386,
1178    Modrm|No_bSuf|No_sSuf|No_xSuf,
1179    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1180      Reg16|Reg32|Reg64 } },
1181  { "bt", 2, 0xfa3, None, Cpu386,
1182    Modrm|No_bSuf|No_sSuf|No_xSuf,
1183    { Reg16|Reg32|Reg64,
1184      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1185  { "bt", 2, 0xfba, 0x4, Cpu386,
1186    Modrm|No_bSuf|No_sSuf|No_xSuf,
1187    { Imm8,
1188      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1189  { "btc", 2, 0xfbb, None, Cpu386,
1190    Modrm|No_bSuf|No_sSuf|No_xSuf,
1191    { Reg16|Reg32|Reg64,
1192      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1193  { "btc", 2, 0xfba, 0x7, Cpu386,
1194    Modrm|No_bSuf|No_sSuf|No_xSuf,
1195    { Imm8,
1196      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1197  { "btr", 2, 0xfb3, None, Cpu386,
1198    Modrm|No_bSuf|No_sSuf|No_xSuf,
1199    { Reg16|Reg32|Reg64,
1200      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1201  { "btr", 2, 0xfba, 0x6, Cpu386,
1202    Modrm|No_bSuf|No_sSuf|No_xSuf,
1203    { Imm8,
1204      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1205  { "bts", 2, 0xfab, None, Cpu386,
1206    Modrm|No_bSuf|No_sSuf|No_xSuf,
1207    { Reg16|Reg32|Reg64,
1208      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1209  { "bts", 2, 0xfba, 0x5, Cpu386,
1210    Modrm|No_bSuf|No_sSuf|No_xSuf,
1211    { Imm8,
1212      Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1213  { "int", 1, 0xcd, None, 0,
1214    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1215    { Imm8 } },
1216  { "int3", 0, 0xcc, None, 0,
1217    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1218    { 0 } },
1219  { "into", 0, 0xce, None, CpuNo64,
1220    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1221    { 0 } },
1222  { "iret", 0, 0xcf, None, 0,
1223    DefaultSize|No_bSuf|No_sSuf|No_xSuf,
1224    { 0 } },
1225  { "rsm", 0, 0xfaa, None, Cpu386,
1226    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1227    { 0 } },
1228  { "bound", 2, 0x62, None, Cpu186|CpuNo64,
1229    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1230    { Reg16|Reg32|Reg64,
1231      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1232  { "hlt", 0, 0xf4, None, 0,
1233    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1234    { 0 } },
1235  { "nop", 1, 0xf1f, 0x0, Cpu686,
1236    Modrm|No_bSuf|No_sSuf|No_xSuf,
1237    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1238  { "nop", 0, 0x90, None, 0,
1239    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1240    { 0 } },
1241  { "arpl", 2, 0x63, None, Cpu286|CpuNo64,
1242    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1243    { Reg16,
1244      Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1245  { "lar", 2, 0xf02, None, Cpu286,
1246    Modrm|No_bSuf|No_sSuf|No_xSuf,
1247    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1248      Reg16|Reg32|Reg64 } },
1249  { "lgdt", 1, 0xf01, 0x2, Cpu286|CpuNo64,
1250    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1251    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1252  { "lgdt", 1, 0xf01, 0x2, Cpu64,
1253    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1254    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1255  { "lidt", 1, 0xf01, 0x3, Cpu286|CpuNo64,
1256    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1257    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1258  { "lidt", 1, 0xf01, 0x3, Cpu64,
1259    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1260    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1261  { "lldt", 1, 0xf00, 0x2, Cpu286,
1262    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1263    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1264  { "lmsw", 1, 0xf01, 0x6, Cpu286,
1265    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1266    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1267  { "lsl", 2, 0xf03, None, Cpu286,
1268    Modrm|No_bSuf|No_sSuf|No_xSuf,
1269    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1270      Reg16|Reg32|Reg64 } },
1271  { "ltr", 1, 0xf00, 0x3, Cpu286,
1272    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1273    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1274  { "sgdt", 1, 0xf01, 0x0, Cpu286|CpuNo64,
1275    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1276    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1277  { "sgdt", 1, 0xf01, 0x0, Cpu64,
1278    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1279    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1280  { "sidt", 1, 0xf01, 0x1, Cpu286|CpuNo64,
1281    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1282    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1283  { "sidt", 1, 0xf01, 0x1, Cpu64,
1284    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1285    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1286  { "sldt", 1, 0xf00, 0x0, Cpu286,
1287    Modrm|No_bSuf|No_sSuf|No_xSuf,
1288    { Reg16|Reg32|Reg64 } },
1289  { "sldt", 1, 0xf00, 0x0, Cpu286,
1290    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1291    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1292  { "smsw", 1, 0xf01, 0x4, Cpu286,
1293    Modrm|No_bSuf|No_sSuf|No_xSuf,
1294    { Reg16|Reg32|Reg64 } },
1295  { "smsw", 1, 0xf01, 0x4, Cpu286,
1296    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1297    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1298  { "str", 1, 0xf00, 0x1, Cpu286,
1299    Modrm|No_bSuf|No_sSuf|No_xSuf,
1300    { Reg16|Reg32|Reg64 } },
1301  { "str", 1, 0xf00, 0x1, Cpu286,
1302    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1303    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1304  { "verr", 1, 0xf00, 0x4, Cpu286,
1305    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1306    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1307  { "verw", 1, 0xf00, 0x5, Cpu286,
1308    Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1309    { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1310  { "fld", 1, 0xd9c0, None, 0,
1311    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1312    { FloatReg } },
1313  { "fld", 1, 0xd9, 0x0, 0,
1314    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1315    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1316  { "fld", 1, 0xd9c0, None, 0,
1317    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1318    { FloatReg } },
1319  { "fld", 1, 0xdb, 0x5, 0,
1320    Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1321    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1322  { "fild", 1, 0xdf, 0x0, 0,
1323    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1324    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1325  { "fild", 1, 0xdf, 0x5, 0,
1326    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1327    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1328  { "fildll", 1, 0xdf, 0x5, 0,
1329    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1330    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1331  { "fldt", 1, 0xdb, 0x5, 0,
1332    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1333    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1334  { "fbld", 1, 0xdf, 0x4, 0,
1335    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1336    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1337  { "fst", 1, 0xddd0, None, 0,
1338    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1339    { FloatReg } },
1340  { "fst", 1, 0xd9, 0x2, 0,
1341    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1342    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1343  { "fst", 1, 0xddd0, None, 0,
1344    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1345    { FloatReg } },
1346  { "fist", 1, 0xdf, 0x2, 0,
1347    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1348    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1349  { "fstp", 1, 0xddd8, None, 0,
1350    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1351    { FloatReg } },
1352  { "fstp", 1, 0xd9, 0x3, 0,
1353    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1354    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1355  { "fstp", 1, 0xddd8, None, 0,
1356    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1357    { FloatReg } },
1358  { "fstp", 1, 0xdb, 0x7, 0,
1359    Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1360    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1361  { "fistp", 1, 0xdf, 0x3, 0,
1362    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1363    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1364  { "fistp", 1, 0xdf, 0x7, 0,
1365    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1366    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1367  { "fistpll", 1, 0xdf, 0x7, 0,
1368    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1369    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1370  { "fstpt", 1, 0xdb, 0x7, 0,
1371    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1372    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1373  { "fbstp", 1, 0xdf, 0x6, 0,
1374    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1375    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1376  { "fxch", 1, 0xd9c8, None, 0,
1377    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1378    { FloatReg } },
1379  { "fxch", 0, 0xd9c9, None, 0,
1380    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1381    { 0 } },
1382  { "fcom", 1, 0xd8d0, None, 0,
1383    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1384    { FloatReg } },
1385  { "fcom", 0, 0xd8d1, None, 0,
1386    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1387    { 0 } },
1388  { "fcom", 1, 0xd8, 0x2, 0,
1389    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1390    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1391  { "fcom", 1, 0xd8d0, None, 0,
1392    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1393    { FloatReg } },
1394  { "ficom", 1, 0xde, 0x2, 0,
1395    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1396    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1397  { "fcomp", 1, 0xd8d8, None, 0,
1398    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1399    { FloatReg } },
1400  { "fcomp", 0, 0xd8d9, None, 0,
1401    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1402    { 0 } },
1403  { "fcomp", 1, 0xd8, 0x3, 0,
1404    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1405    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1406  { "fcomp", 1, 0xd8d8, None, 0,
1407    ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1408    { FloatReg } },
1409  { "ficomp", 1, 0xde, 0x3, 0,
1410    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1411    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1412  { "fcompp", 0, 0xded9, None, 0,
1413    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1414    { 0 } },
1415  { "fucom", 1, 0xdde0, None, Cpu286,
1416    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1417    { FloatReg } },
1418  { "fucom", 0, 0xdde1, None, Cpu286,
1419    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1420    { 0 } },
1421  { "fucomp", 1, 0xdde8, None, Cpu286,
1422    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1423    { FloatReg } },
1424  { "fucomp", 0, 0xdde9, None, Cpu286,
1425    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1426    { 0 } },
1427  { "fucompp", 0, 0xdae9, None, Cpu286,
1428    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1429    { 0 } },
1430  { "ftst", 0, 0xd9e4, None, 0,
1431    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1432    { 0 } },
1433  { "fxam", 0, 0xd9e5, None, 0,
1434    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1435    { 0 } },
1436  { "fld1", 0, 0xd9e8, None, 0,
1437    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1438    { 0 } },
1439  { "fldl2t", 0, 0xd9e9, None, 0,
1440    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1441    { 0 } },
1442  { "fldl2e", 0, 0xd9ea, None, 0,
1443    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1444    { 0 } },
1445  { "fldpi", 0, 0xd9eb, None, 0,
1446    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1447    { 0 } },
1448  { "fldlg2", 0, 0xd9ec, None, 0,
1449    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1450    { 0 } },
1451  { "fldln2", 0, 0xd9ed, None, 0,
1452    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1453    { 0 } },
1454  { "fldz", 0, 0xd9ee, None, 0,
1455    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1456    { 0 } },
1457  { "fadd", 2, 0xd8c0, None, 0,
1458    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1459    { FloatReg,
1460      FloatAcc } },
1461  { "fadd", 1, 0xd8c0, None, 0,
1462    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1463    { FloatReg } },
1464#if SYSV386_COMPAT
1465  { "fadd", 0, 0xdec1, None, 0,
1466    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1467    { 0 } },
1468#endif
1469  { "fadd", 1, 0xd8, 0x0, 0,
1470    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1471    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1472  { "fiadd", 1, 0xde, 0x0, 0,
1473    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1474    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1475  { "faddp", 2, 0xdec0, None, 0,
1476    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1477    { FloatAcc,
1478      FloatReg } },
1479  { "faddp", 1, 0xdec0, None, 0,
1480    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1481    { FloatReg } },
1482  { "faddp", 0, 0xdec1, None, 0,
1483    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1484    { 0 } },
1485  { "faddp", 2, 0xdec0, None, 0,
1486    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1487    { FloatReg,
1488      FloatAcc } },
1489  { "fsub", 1, 0xd8e0, None, 0,
1490    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1491    { FloatReg } },
1492#if SYSV386_COMPAT
1493  { "fsub", 2, 0xd8e0, None, 0,
1494    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1495    { FloatReg,
1496      FloatAcc } },
1497  { "fsub", 0, 0xdee1, None, 0,
1498    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1499    { 0 } },
1500#else
1501  { "fsub", 2, 0xd8e0, None, 0,
1502    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1503    { FloatReg,
1504      FloatAcc } },
1505#endif
1506  { "fsub", 1, 0xd8, 0x4, 0,
1507    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1508    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1509  { "fisub", 1, 0xde, 0x4, 0,
1510    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1511    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1512#if SYSV386_COMPAT
1513  { "fsubp", 2, 0xdee0, None, 0,
1514    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1515    { FloatAcc,
1516      FloatReg } },
1517  { "fsubp", 1, 0xdee0, None, 0,
1518    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1519    { FloatReg } },
1520  { "fsubp", 0, 0xdee1, None, 0,
1521    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1522    { 0 } },
1523#if OLDGCC_COMPAT
1524  { "fsubp", 2, 0xdee0, None, 0,
1525    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1526    { FloatReg,
1527      FloatAcc } },
1528#endif
1529#else
1530  { "fsubp", 2, 0xdee8, None, 0,
1531    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1532    { FloatAcc,
1533      FloatReg } },
1534  { "fsubp", 1, 0xdee8, None, 0,
1535    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1536    { FloatReg } },
1537  { "fsubp", 0, 0xdee9, None, 0,
1538    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1539    { 0 } },
1540#endif
1541  { "fsubr", 1, 0xd8e8, None, 0,
1542    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1543    { FloatReg } },
1544#if SYSV386_COMPAT
1545  { "fsubr", 2, 0xd8e8, None, 0,
1546    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1547    { FloatReg,
1548      FloatAcc } },
1549  { "fsubr", 0, 0xdee9, None, 0,
1550    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1551    { 0 } },
1552#else
1553  { "fsubr", 2, 0xd8e8, None, 0,
1554    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1555    { FloatReg,
1556      FloatAcc } },
1557#endif
1558  { "fsubr", 1, 0xd8, 0x5, 0,
1559    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1560    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1561  { "fisubr", 1, 0xde, 0x5, 0,
1562    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1563    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1564#if SYSV386_COMPAT
1565  { "fsubrp", 2, 0xdee8, None, 0,
1566    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1567    { FloatAcc,
1568      FloatReg } },
1569  { "fsubrp", 1, 0xdee8, None, 0,
1570    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1571    { FloatReg } },
1572  { "fsubrp", 0, 0xdee9, None, 0,
1573    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1574    { 0 } },
1575#if OLDGCC_COMPAT
1576  { "fsubrp", 2, 0xdee8, None, 0,
1577    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1578    { FloatReg,
1579      FloatAcc } },
1580#endif
1581#else
1582  { "fsubrp", 2, 0xdee0, None, 0,
1583    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1584    { FloatAcc,
1585      FloatReg } },
1586  { "fsubrp", 1, 0xdee0, None, 0,
1587    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1588    { FloatReg } },
1589  { "fsubrp", 0, 0xdee1, None, 0,
1590    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1591    { 0 } },
1592#endif
1593  { "fmul", 2, 0xd8c8, None, 0,
1594    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1595    { FloatReg,
1596      FloatAcc } },
1597  { "fmul", 1, 0xd8c8, None, 0,
1598    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1599    { FloatReg } },
1600#if SYSV386_COMPAT
1601  { "fmul", 0, 0xdec9, None, 0,
1602    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1603    { 0 } },
1604#endif
1605  { "fmul", 1, 0xd8, 0x1, 0,
1606    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1607    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1608  { "fimul", 1, 0xde, 0x1, 0,
1609    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1610    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1611  { "fmulp", 2, 0xdec8, None, 0,
1612    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1613    { FloatAcc,
1614      FloatReg } },
1615  { "fmulp", 1, 0xdec8, None, 0,
1616    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1617    { FloatReg } },
1618  { "fmulp", 0, 0xdec9, None, 0,
1619    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1620    { 0 } },
1621  { "fmulp", 2, 0xdec8, None, 0,
1622    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1623    { FloatReg,
1624      FloatAcc } },
1625  { "fdiv", 1, 0xd8f0, None, 0,
1626    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1627    { FloatReg } },
1628#if SYSV386_COMPAT
1629  { "fdiv", 2, 0xd8f0, None, 0,
1630    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1631    { FloatReg,
1632      FloatAcc } },
1633  { "fdiv", 0, 0xdef1, None, 0,
1634    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1635    { 0 } },
1636#else
1637  { "fdiv", 2, 0xd8f0, None, 0,
1638    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1639    { FloatReg,
1640      FloatAcc } },
1641#endif
1642  { "fdiv", 1, 0xd8, 0x6, 0,
1643    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1644    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1645  { "fidiv", 1, 0xde, 0x6, 0,
1646    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1647    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1648#if SYSV386_COMPAT
1649  { "fdivp", 2, 0xdef0, None, 0,
1650    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1651    { FloatAcc,
1652      FloatReg } },
1653  { "fdivp", 1, 0xdef0, None, 0,
1654    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1655    { FloatReg } },
1656  { "fdivp", 0, 0xdef1, None, 0,
1657    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1658    { 0 } },
1659#if OLDGCC_COMPAT
1660  { "fdivp", 2, 0xdef0, None, 0,
1661    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1662    { FloatReg,
1663      FloatAcc } },
1664#endif
1665#else
1666  { "fdivp", 2, 0xdef8, None, 0,
1667    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1668    { FloatAcc,
1669      FloatReg } },
1670  { "fdivp", 1, 0xdef8, None, 0,
1671    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1672    { FloatReg } },
1673  { "fdivp", 0, 0xdef9, None, 0,
1674    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1675    { 0 } },
1676#endif
1677  { "fdivr", 1, 0xd8f8, None, 0,
1678    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1679    { FloatReg } },
1680#if SYSV386_COMPAT
1681  { "fdivr", 2, 0xd8f8, None, 0,
1682    ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1683    { FloatReg,
1684      FloatAcc } },
1685  { "fdivr", 0, 0xdef9, None, 0,
1686    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1687    { 0 } },
1688#else
1689  { "fdivr", 2, 0xd8f8, None, 0,
1690    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1691    { FloatReg,
1692      FloatAcc } },
1693#endif
1694  { "fdivr", 1, 0xd8, 0x7, 0,
1695    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1696    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1697  { "fidivr", 1, 0xde, 0x7, 0,
1698    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1699    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1700#if SYSV386_COMPAT
1701  { "fdivrp", 2, 0xdef8, None, 0,
1702    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1703    { FloatAcc,
1704      FloatReg } },
1705  { "fdivrp", 1, 0xdef8, None, 0,
1706    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1707    { FloatReg } },
1708  { "fdivrp", 0, 0xdef9, None, 0,
1709    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1710    { 0 } },
1711#if OLDGCC_COMPAT
1712  { "fdivrp", 2, 0xdef8, None, 0,
1713    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1714    { FloatReg,
1715      FloatAcc } },
1716#endif
1717#else
1718  { "fdivrp", 2, 0xdef0, None, 0,
1719    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1720    { FloatAcc,
1721      FloatReg } },
1722  { "fdivrp", 1, 0xdef0, None, 0,
1723    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1724    { FloatReg } },
1725  { "fdivrp", 0, 0xdef1, None, 0,
1726    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1727    { 0 } },
1728#endif
1729  { "f2xm1", 0, 0xd9f0, None, 0,
1730    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1731    { 0 } },
1732  { "fyl2x", 0, 0xd9f1, None, 0,
1733    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1734    { 0 } },
1735  { "fptan", 0, 0xd9f2, None, 0,
1736    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1737    { 0 } },
1738  { "fpatan", 0, 0xd9f3, None, 0,
1739    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1740    { 0 } },
1741  { "fxtract", 0, 0xd9f4, None, 0,
1742    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1743    { 0 } },
1744  { "fprem1", 0, 0xd9f5, None, Cpu286,
1745    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1746    { 0 } },
1747  { "fdecstp", 0, 0xd9f6, None, 0,
1748    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1749    { 0 } },
1750  { "fincstp", 0, 0xd9f7, None, 0,
1751    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1752    { 0 } },
1753  { "fprem", 0, 0xd9f8, None, 0,
1754    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1755    { 0 } },
1756  { "fyl2xp1", 0, 0xd9f9, None, 0,
1757    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1758    { 0 } },
1759  { "fsqrt", 0, 0xd9fa, None, 0,
1760    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1761    { 0 } },
1762  { "fsincos", 0, 0xd9fb, None, Cpu286,
1763    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1764    { 0 } },
1765  { "frndint", 0, 0xd9fc, None, 0,
1766    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1767    { 0 } },
1768  { "fscale", 0, 0xd9fd, None, 0,
1769    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1770    { 0 } },
1771  { "fsin", 0, 0xd9fe, None, Cpu286,
1772    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1773    { 0 } },
1774  { "fcos", 0, 0xd9ff, None, Cpu286,
1775    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1776    { 0 } },
1777  { "fchs", 0, 0xd9e0, None, 0,
1778    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1779    { 0 } },
1780  { "fabs", 0, 0xd9e1, None, 0,
1781    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1782    { 0 } },
1783  { "fninit", 0, 0xdbe3, None, 0,
1784    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1785    { 0 } },
1786  { "finit", 0, 0xdbe3, None, 0,
1787    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1788    { 0 } },
1789  { "fldcw", 1, 0xd9, 0x5, 0,
1790    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1791    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1792  { "fnstcw", 1, 0xd9, 0x7, 0,
1793    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1794    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1795  { "fstcw", 1, 0xd9, 0x7, 0,
1796    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1797    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1798  { "fnstsw", 1, 0xdfe0, None, 0,
1799    IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1800    { Acc } },
1801  { "fnstsw", 1, 0xdd, 0x7, 0,
1802    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1803    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1804  { "fnstsw", 0, 0xdfe0, None, 0,
1805    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1806    { 0 } },
1807  { "fstsw", 1, 0xdfe0, None, 0,
1808    IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1809    { Acc } },
1810  { "fstsw", 1, 0xdd, 0x7, 0,
1811    Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1812    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1813  { "fstsw", 0, 0xdfe0, None, 0,
1814    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1815    { 0 } },
1816  { "fnclex", 0, 0xdbe2, None, 0,
1817    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1818    { 0 } },
1819  { "fclex", 0, 0xdbe2, None, 0,
1820    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1821    { 0 } },
1822  { "fnstenv", 1, 0xd9, 0x6, 0,
1823    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1824    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1825  { "fstenv", 1, 0xd9, 0x6, 0,
1826    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait,
1827    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1828  { "fldenv", 1, 0xd9, 0x4, 0,
1829    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1830    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1831  { "fnsave", 1, 0xdd, 0x6, 0,
1832    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1833    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1834  { "fsave", 1, 0xdd, 0x6, 0,
1835    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait,
1836    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1837  { "frstor", 1, 0xdd, 0x4, 0,
1838    Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1839    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1840  { "ffree", 1, 0xddc0, None, 0,
1841    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1842    { FloatReg } },
1843  { "ffreep", 1, 0xdfc0, None, Cpu686,
1844    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1845    { FloatReg } },
1846  { "fnop", 0, 0xd9d0, None, 0,
1847    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1848    { 0 } },
1849  { "fwait", 0, 0x9b, None, 0,
1850    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1851    { 0 } },
1852  { "addr16", 0, 0x67, None, Cpu386|CpuNo64,
1853    Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1854    { 0 } },
1855  { "addr32", 0, 0x67, None, Cpu386,
1856    Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1857    { 0 } },
1858  { "aword", 0, 0x67, None, Cpu386|CpuNo64,
1859    Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1860    { 0 } },
1861  { "adword", 0, 0x67, None, Cpu386,
1862    Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1863    { 0 } },
1864  { "data16", 0, 0x66, None, Cpu386,
1865    Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1866    { 0 } },
1867  { "data32", 0, 0x66, None, Cpu386|CpuNo64,
1868    Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1869    { 0 } },
1870  { "word", 0, 0x66, None, Cpu386,
1871    Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1872    { 0 } },
1873  { "dword", 0, 0x66, None, Cpu386|CpuNo64,
1874    Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1875    { 0 } },
1876  { "lock", 0, 0xf0, None, 0,
1877    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1878    { 0 } },
1879  { "wait", 0, 0x9b, None, 0,
1880    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1881    { 0 } },
1882  { "cs", 0, 0x2e, None, 0,
1883    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1884    { 0 } },
1885  { "ds", 0, 0x3e, None, 0,
1886    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1887    { 0 } },
1888  { "es", 0, 0x26, None, CpuNo64,
1889    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1890    { 0 } },
1891  { "fs", 0, 0x64, None, Cpu386,
1892    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1893    { 0 } },
1894  { "gs", 0, 0x65, None, Cpu386,
1895    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1896    { 0 } },
1897  { "ss", 0, 0x36, None, CpuNo64,
1898    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1899    { 0 } },
1900  { "rep", 0, 0xf3, None, 0,
1901    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1902    { 0 } },
1903  { "repe", 0, 0xf3, None, 0,
1904    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1905    { 0 } },
1906  { "repz", 0, 0xf3, None, 0,
1907    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1908    { 0 } },
1909  { "repne", 0, 0xf2, None, 0,
1910    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1911    { 0 } },
1912  { "repnz", 0, 0xf2, None, 0,
1913    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1914    { 0 } },
1915  { "ht", 0, 0x3e, None, 0,
1916    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1917    { 0 } },
1918  { "hnt", 0, 0x2e, None, 0,
1919    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1920    { 0 } },
1921  { "rex", 0, 0x40, None, Cpu64,
1922    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1923    { 0 } },
1924  { "rexz", 0, 0x41, None, Cpu64,
1925    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1926    { 0 } },
1927  { "rexy", 0, 0x42, None, Cpu64,
1928    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1929    { 0 } },
1930  { "rexyz", 0, 0x43, None, Cpu64,
1931    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1932    { 0 } },
1933  { "rexx", 0, 0x44, None, Cpu64,
1934    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1935    { 0 } },
1936  { "rexxz", 0, 0x45, None, Cpu64,
1937    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1938    { 0 } },
1939  { "rexxy", 0, 0x46, None, Cpu64,
1940    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1941    { 0 } },
1942  { "rexxyz", 0, 0x47, None, Cpu64,
1943    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1944    { 0 } },
1945  { "rex64", 0, 0x48, None, Cpu64,
1946    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1947    { 0 } },
1948  { "rex64z", 0, 0x49, None, Cpu64,
1949    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1950    { 0 } },
1951  { "rex64y", 0, 0x4a, None, Cpu64,
1952    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1953    { 0 } },
1954  { "rex64yz", 0, 0x4b, None, Cpu64,
1955    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1956    { 0 } },
1957  { "rex64x", 0, 0x4c, None, Cpu64,
1958    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1959    { 0 } },
1960  { "rex64xz", 0, 0x4d, None, Cpu64,
1961    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1962    { 0 } },
1963  { "rex64xy", 0, 0x4e, None, Cpu64,
1964    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1965    { 0 } },
1966  { "rex64xyz", 0, 0x4f, None, Cpu64,
1967    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1968    { 0 } },
1969  { "rex.b", 0, 0x41, None, Cpu64,
1970    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1971    { 0 } },
1972  { "rex.x", 0, 0x42, None, Cpu64,
1973    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1974    { 0 } },
1975  { "rex.xb", 0, 0x43, None, Cpu64,
1976    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1977    { 0 } },
1978  { "rex.r", 0, 0x44, None, Cpu64,
1979    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1980    { 0 } },
1981  { "rex.rb", 0, 0x45, None, Cpu64,
1982    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1983    { 0 } },
1984  { "rex.rx", 0, 0x46, None, Cpu64,
1985    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1986    { 0 } },
1987  { "rex.rxb", 0, 0x47, None, Cpu64,
1988    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1989    { 0 } },
1990  { "rex.w", 0, 0x48, None, Cpu64,
1991    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1992    { 0 } },
1993  { "rex.wb", 0, 0x49, None, Cpu64,
1994    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1995    { 0 } },
1996  { "rex.wx", 0, 0x4a, None, Cpu64,
1997    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1998    { 0 } },
1999  { "rex.wxb", 0, 0x4b, None, Cpu64,
2000    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
2001    { 0 } },
2002  { "rex.wr", 0, 0x4c, None, Cpu64,
2003    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
2004    { 0 } },
2005  { "rex.wrb", 0, 0x4d, None, Cpu64,
2006    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
2007    { 0 } },
2008  { "rex.wrx", 0, 0x4e, None, Cpu64,
2009    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
2010    { 0 } },
2011  { "rex.wrxb", 0, 0x4f, None, Cpu64,
2012    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
2013    { 0 } },
2014  { "bswap", 1, 0xfc8, None, Cpu486,
2015    ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2016    { Reg32|Reg64 } },
2017  { "xadd", 2, 0xfc0, None, Cpu486,
2018    W|Modrm|No_sSuf|No_xSuf,
2019    { Reg8|Reg16|Reg32|Reg64,
2020      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2021  { "cmpxchg", 2, 0xfb0, None, Cpu486,
2022    W|Modrm|No_sSuf|No_xSuf,
2023    { Reg8|Reg16|Reg32|Reg64,
2024      Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2025  { "invd", 0, 0xf08, None, Cpu486,
2026    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2027    { 0 } },
2028  { "wbinvd", 0, 0xf09, None, Cpu486,
2029    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2030    { 0 } },
2031  { "invlpg", 1, 0xf01, 0x7, Cpu486,
2032    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2033    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2034  { "cpuid", 0, 0xfa2, None, Cpu486,
2035    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2036    { 0 } },
2037  { "wrmsr", 0, 0xf30, None, Cpu586,
2038    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2039    { 0 } },
2040  { "rdtsc", 0, 0xf31, None, Cpu586,
2041    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2042    { 0 } },
2043  { "rdmsr", 0, 0xf32, None, Cpu586,
2044    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2045    { 0 } },
2046  { "cmpxchg8b", 1, 0xfc7, 0x1, Cpu586,
2047    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2048    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2049  { "sysenter", 0, 0xf34, None, Cpu686,
2050    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2051    { 0 } },
2052  { "sysexit", 0, 0xf35, None, Cpu686,
2053    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2054    { 0 } },
2055  { "fxsave", 1, 0xfae, 0x0, Cpu686,
2056    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2057    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2058  { "fxrstor", 1, 0xfae, 0x1, Cpu686,
2059    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2060    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2061  { "rdpmc", 0, 0xf33, None, Cpu686,
2062    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2063    { 0 } },
2064  { "ud2", 0, 0xf0b, None, Cpu686,
2065    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2066    { 0 } },
2067  { "ud2a", 0, 0xf0b, None, Cpu686,
2068    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2069    { 0 } },
2070  { "ud2b", 0, 0xfb9, None, Cpu686,
2071    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2072    { 0 } },
2073  { "cmovo", 2, 0xf40, None, Cpu686,
2074    Modrm|No_bSuf|No_sSuf|No_xSuf,
2075    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2076      Reg16|Reg32|Reg64 } },
2077  { "cmovno", 2, 0xf41, None, Cpu686,
2078    Modrm|No_bSuf|No_sSuf|No_xSuf,
2079    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2080      Reg16|Reg32|Reg64 } },
2081  { "cmovb", 2, 0xf42, None, Cpu686,
2082    Modrm|No_bSuf|No_sSuf|No_xSuf,
2083    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2084      Reg16|Reg32|Reg64 } },
2085  { "cmovc", 2, 0xf42, None, Cpu686,
2086    Modrm|No_bSuf|No_sSuf|No_xSuf,
2087    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2088      Reg16|Reg32|Reg64 } },
2089  { "cmovnae", 2, 0xf42, None, Cpu686,
2090    Modrm|No_bSuf|No_sSuf|No_xSuf,
2091    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2092      Reg16|Reg32|Reg64 } },
2093  { "cmovae", 2, 0xf43, None, Cpu686,
2094    Modrm|No_bSuf|No_sSuf|No_xSuf,
2095    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2096      Reg16|Reg32|Reg64 } },
2097  { "cmovnc", 2, 0xf43, None, Cpu686,
2098    Modrm|No_bSuf|No_sSuf|No_xSuf,
2099    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2100      Reg16|Reg32|Reg64 } },
2101  { "cmovnb", 2, 0xf43, None, Cpu686,
2102    Modrm|No_bSuf|No_sSuf|No_xSuf,
2103    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2104      Reg16|Reg32|Reg64 } },
2105  { "cmove", 2, 0xf44, None, Cpu686,
2106    Modrm|No_bSuf|No_sSuf|No_xSuf,
2107    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2108      Reg16|Reg32|Reg64 } },
2109  { "cmovz", 2, 0xf44, None, Cpu686,
2110    Modrm|No_bSuf|No_sSuf|No_xSuf,
2111    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2112      Reg16|Reg32|Reg64 } },
2113  { "cmovne", 2, 0xf45, None, Cpu686,
2114    Modrm|No_bSuf|No_sSuf|No_xSuf,
2115    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2116      Reg16|Reg32|Reg64 } },
2117  { "cmovnz", 2, 0xf45, None, Cpu686,
2118    Modrm|No_bSuf|No_sSuf|No_xSuf,
2119    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2120      Reg16|Reg32|Reg64 } },
2121  { "cmovbe", 2, 0xf46, None, Cpu686,
2122    Modrm|No_bSuf|No_sSuf|No_xSuf,
2123    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2124      Reg16|Reg32|Reg64 } },
2125  { "cmovna", 2, 0xf46, None, Cpu686,
2126    Modrm|No_bSuf|No_sSuf|No_xSuf,
2127    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2128      Reg16|Reg32|Reg64 } },
2129  { "cmova", 2, 0xf47, None, Cpu686,
2130    Modrm|No_bSuf|No_sSuf|No_xSuf,
2131    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2132      Reg16|Reg32|Reg64 } },
2133  { "cmovnbe", 2, 0xf47, None, Cpu686,
2134    Modrm|No_bSuf|No_sSuf|No_xSuf,
2135    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2136      Reg16|Reg32|Reg64 } },
2137  { "cmovs", 2, 0xf48, None, Cpu686,
2138    Modrm|No_bSuf|No_sSuf|No_xSuf,
2139    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2140      Reg16|Reg32|Reg64 } },
2141  { "cmovns", 2, 0xf49, None, Cpu686,
2142    Modrm|No_bSuf|No_sSuf|No_xSuf,
2143    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2144      Reg16|Reg32|Reg64 } },
2145  { "cmovp", 2, 0xf4a, None, Cpu686,
2146    Modrm|No_bSuf|No_sSuf|No_xSuf,
2147    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2148      Reg16|Reg32|Reg64 } },
2149  { "cmovnp", 2, 0xf4b, None, Cpu686,
2150    Modrm|No_bSuf|No_sSuf|No_xSuf,
2151    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2152      Reg16|Reg32|Reg64 } },
2153  { "cmovl", 2, 0xf4c, None, Cpu686,
2154    Modrm|No_bSuf|No_sSuf|No_xSuf,
2155    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2156      Reg16|Reg32|Reg64 } },
2157  { "cmovnge", 2, 0xf4c, None, Cpu686,
2158    Modrm|No_bSuf|No_sSuf|No_xSuf,
2159    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2160      Reg16|Reg32|Reg64 } },
2161  { "cmovge", 2, 0xf4d, None, Cpu686,
2162    Modrm|No_bSuf|No_sSuf|No_xSuf,
2163    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2164      Reg16|Reg32|Reg64 } },
2165  { "cmovnl", 2, 0xf4d, None, Cpu686,
2166    Modrm|No_bSuf|No_sSuf|No_xSuf,
2167    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2168      Reg16|Reg32|Reg64 } },
2169  { "cmovle", 2, 0xf4e, None, Cpu686,
2170    Modrm|No_bSuf|No_sSuf|No_xSuf,
2171    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2172      Reg16|Reg32|Reg64 } },
2173  { "cmovng", 2, 0xf4e, None, Cpu686,
2174    Modrm|No_bSuf|No_sSuf|No_xSuf,
2175    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2176      Reg16|Reg32|Reg64 } },
2177  { "cmovg", 2, 0xf4f, None, Cpu686,
2178    Modrm|No_bSuf|No_sSuf|No_xSuf,
2179    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2180      Reg16|Reg32|Reg64 } },
2181  { "cmovnle", 2, 0xf4f, None, Cpu686,
2182    Modrm|No_bSuf|No_sSuf|No_xSuf,
2183    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2184      Reg16|Reg32|Reg64 } },
2185  { "fcmovb", 2, 0xdac0, None, Cpu686,
2186    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2187    { FloatReg,
2188      FloatAcc } },
2189  { "fcmovnae", 2, 0xdac0, None, Cpu686,
2190    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2191    { FloatReg,
2192      FloatAcc } },
2193  { "fcmove", 2, 0xdac8, None, Cpu686,
2194    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2195    { FloatReg,
2196      FloatAcc } },
2197  { "fcmovbe", 2, 0xdad0, None, Cpu686,
2198    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2199    { FloatReg,
2200      FloatAcc } },
2201  { "fcmovna", 2, 0xdad0, None, Cpu686,
2202    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2203    { FloatReg,
2204      FloatAcc } },
2205  { "fcmovu", 2, 0xdad8, None, Cpu686,
2206    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2207    { FloatReg,
2208      FloatAcc } },
2209  { "fcmovae", 2, 0xdbc0, None, Cpu686,
2210    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2211    { FloatReg,
2212      FloatAcc } },
2213  { "fcmovnb", 2, 0xdbc0, None, Cpu686,
2214    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2215    { FloatReg,
2216      FloatAcc } },
2217  { "fcmovne", 2, 0xdbc8, None, Cpu686,
2218    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2219    { FloatReg,
2220      FloatAcc } },
2221  { "fcmova", 2, 0xdbd0, None, Cpu686,
2222    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2223    { FloatReg,
2224      FloatAcc } },
2225  { "fcmovnbe", 2, 0xdbd0, None, Cpu686,
2226    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2227    { FloatReg,
2228      FloatAcc } },
2229  { "fcmovnu", 2, 0xdbd8, None, Cpu686,
2230    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2231    { FloatReg,
2232      FloatAcc } },
2233  { "fcomi", 2, 0xdbf0, None, Cpu686,
2234    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2235    { FloatReg,
2236      FloatAcc } },
2237  { "fcomi", 0, 0xdbf1, None, Cpu686,
2238    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2239    { 0 } },
2240  { "fcomi", 1, 0xdbf0, None, Cpu686,
2241    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2242    { FloatReg } },
2243  { "fucomi", 2, 0xdbe8, None, Cpu686,
2244    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2245    { FloatReg,
2246      FloatAcc } },
2247  { "fucomi", 0, 0xdbe9, None, Cpu686,
2248    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2249    { 0 } },
2250  { "fucomi", 1, 0xdbe8, None, Cpu686,
2251    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2252    { FloatReg } },
2253  { "fcomip", 2, 0xdff0, None, Cpu686,
2254    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2255    { FloatReg,
2256      FloatAcc } },
2257  { "fcompi", 2, 0xdff0, None, Cpu686,
2258    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2259    { FloatReg,
2260      FloatAcc } },
2261  { "fcompi", 0, 0xdff1, None, Cpu686,
2262    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2263    { 0 } },
2264  { "fcompi", 1, 0xdff0, None, Cpu686,
2265    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2266    { FloatReg } },
2267  { "fucomip", 2, 0xdfe8, None, Cpu686,
2268    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2269    { FloatReg,
2270      FloatAcc } },
2271  { "fucompi", 2, 0xdfe8, None, Cpu686,
2272    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2273    { FloatReg,
2274      FloatAcc } },
2275  { "fucompi", 0, 0xdfe9, None, Cpu686,
2276    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2277    { 0 } },
2278  { "fucompi", 1, 0xdfe8, None, Cpu686,
2279    ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2280    { FloatReg } },
2281  { "movnti", 2, 0xfc3, None, CpuP4,
2282    Modrm|No_bSuf|No_sSuf|No_xSuf,
2283    { Reg16|Reg32|Reg64,
2284      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2285  { "clflush", 1, 0xfae, 0x7, CpuP4,
2286    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2287    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2288  { "lfence", 0, 0xfae, 0xe8, CpuP4,
2289    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2290    { 0 } },
2291  { "mfence", 0, 0xfae, 0xf0, CpuP4,
2292    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2293    { 0 } },
2294  { "pause", 0, 0xf390, None, CpuP4,
2295    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2296    { 0 } },
2297  { "emms", 0, 0xf77, None, CpuMMX,
2298    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2299    { 0 } },
2300  { "movd", 2, 0xf6e, None, CpuMMX,
2301    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2302    { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2303      RegMMX } },
2304  { "movd", 2, 0xf7e, None, CpuMMX,
2305    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2306    { RegMMX,
2307      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2308  { "movd", 2, 0x660f6e, None, CpuSSE2,
2309    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2310    { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2311      RegXMM } },
2312  { "movd", 2, 0x660f7e, None, CpuSSE2,
2313    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2314    { RegXMM,
2315      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2316  { "movq", 2, 0xf6f, None, CpuMMX,
2317    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2318    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2319      RegMMX } },
2320  { "movq", 2, 0xf7f, None, CpuMMX,
2321    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2322    { RegMMX,
2323      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } },
2324  { "movq", 2, 0xf30f7e, None, CpuSSE2,
2325    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2326    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2327      RegXMM } },
2328  { "movq", 2, 0x660fd6, None, CpuSSE2,
2329    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2330    { RegXMM,
2331      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
2332  { "movq", 2, 0xf6e, None, Cpu64,
2333    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2334    { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2335      RegMMX } },
2336  { "movq", 2, 0xf7e, None, Cpu64,
2337    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2338    { RegMMX,
2339      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2340  { "movq", 2, 0x660f6e, None, Cpu64,
2341    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2342    { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2343      RegXMM } },
2344  { "movq", 2, 0x660f7e, None, Cpu64,
2345    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2346    { RegXMM,
2347      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2348  { "movq", 2, 0xa0, None, Cpu64,
2349    D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2350    { Disp64,
2351      Acc } },
2352  { "movq", 2, 0x88, None, Cpu64,
2353    D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2354    { Reg64,
2355      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2356  { "movq", 2, 0xc6, 0x0, Cpu64,
2357    W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2358    { Imm32S,
2359      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2360  { "movq", 2, 0xb0, None, Cpu64,
2361    W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2362    { Imm64,
2363      Reg64 } },
2364  { "movq", 2, 0x8c, None, Cpu64,
2365    Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2366    { SReg2|SReg3,
2367      Reg64|RegMem } },
2368  { "movq", 2, 0x8e, None, Cpu64,
2369    Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2370    { Reg64,
2371      SReg2|SReg3 } },
2372  { "movq", 2, 0xf20, None, Cpu64,
2373    D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2374    { Control,
2375      Reg64|RegMem } },
2376  { "movq", 2, 0xf21, None, Cpu64,
2377    D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2378    { Debug,
2379      Reg64|RegMem } },
2380  { "packssdw", 2, 0xf6b, None, CpuMMX,
2381    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2382    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2383      RegMMX } },
2384  { "packssdw", 2, 0x660f6b, None, CpuSSE2,
2385    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2386    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2387      RegXMM } },
2388  { "packsswb", 2, 0xf63, None, CpuMMX,
2389    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2390    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2391      RegMMX } },
2392  { "packsswb", 2, 0x660f63, None, CpuSSE2,
2393    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2394    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2395      RegXMM } },
2396  { "packuswb", 2, 0xf67, None, CpuMMX,
2397    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2398    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2399      RegMMX } },
2400  { "packuswb", 2, 0x660f67, None, CpuSSE2,
2401    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2402    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2403      RegXMM } },
2404  { "paddb", 2, 0xffc, None, CpuMMX,
2405    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2406    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2407      RegMMX } },
2408  { "paddb", 2, 0x660ffc, None, CpuSSE2,
2409    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2410    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2411      RegXMM } },
2412  { "paddw", 2, 0xffd, None, CpuMMX,
2413    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2414    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2415      RegMMX } },
2416  { "paddw", 2, 0x660ffd, None, CpuSSE2,
2417    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2418    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2419      RegXMM } },
2420  { "paddd", 2, 0xffe, None, CpuMMX,
2421    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2422    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2423      RegMMX } },
2424  { "paddd", 2, 0x660ffe, None, CpuSSE2,
2425    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2426    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2427      RegXMM } },
2428  { "paddq", 2, 0xfd4, None, CpuSSE2,
2429    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2430    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2431      RegMMX } },
2432  { "paddq", 2, 0x660fd4, None, CpuSSE2,
2433    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2434    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2435      RegXMM } },
2436  { "paddsb", 2, 0xfec, None, CpuMMX,
2437    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2438    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2439      RegMMX } },
2440  { "paddsb", 2, 0x660fec, None, CpuSSE2,
2441    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2442    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2443      RegXMM } },
2444  { "paddsw", 2, 0xfed, None, CpuMMX,
2445    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2446    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2447      RegMMX } },
2448  { "paddsw", 2, 0x660fed, None, CpuSSE2,
2449    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2450    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2451      RegXMM } },
2452  { "paddusb", 2, 0xfdc, None, CpuMMX,
2453    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2454    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2455      RegMMX } },
2456  { "paddusb", 2, 0x660fdc, None, CpuSSE2,
2457    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2458    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2459      RegXMM } },
2460  { "paddusw", 2, 0xfdd, None, CpuMMX,
2461    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2462    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2463      RegMMX } },
2464  { "paddusw", 2, 0x660fdd, None, CpuSSE2,
2465    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2466    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2467      RegXMM } },
2468  { "pand", 2, 0xfdb, None, CpuMMX,
2469    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2470    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2471      RegMMX } },
2472  { "pand", 2, 0x660fdb, None, CpuSSE2,
2473    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2474    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2475      RegXMM } },
2476  { "pandn", 2, 0xfdf, None, CpuMMX,
2477    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2478    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2479      RegMMX } },
2480  { "pandn", 2, 0x660fdf, None, CpuSSE2,
2481    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2482    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2483      RegXMM } },
2484  { "pcmpeqb", 2, 0xf74, None, CpuMMX,
2485    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2486    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2487      RegMMX } },
2488  { "pcmpeqb", 2, 0x660f74, None, CpuSSE2,
2489    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2490    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2491      RegXMM } },
2492  { "pcmpeqw", 2, 0xf75, None, CpuMMX,
2493    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2494    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2495      RegMMX } },
2496  { "pcmpeqw", 2, 0x660f75, None, CpuSSE2,
2497    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2498    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2499      RegXMM } },
2500  { "pcmpeqd", 2, 0xf76, None, CpuMMX,
2501    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2502    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2503      RegMMX } },
2504  { "pcmpeqd", 2, 0x660f76, None, CpuSSE2,
2505    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2506    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2507      RegXMM } },
2508  { "pcmpgtb", 2, 0xf64, None, CpuMMX,
2509    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2510    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2511      RegMMX } },
2512  { "pcmpgtb", 2, 0x660f64, None, CpuSSE2,
2513    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2514    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2515      RegXMM } },
2516  { "pcmpgtw", 2, 0xf65, None, CpuMMX,
2517    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2518    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2519      RegMMX } },
2520  { "pcmpgtw", 2, 0x660f65, None, CpuSSE2,
2521    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2522    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2523      RegXMM } },
2524  { "pcmpgtd", 2, 0xf66, None, CpuMMX,
2525    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2526    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2527      RegMMX } },
2528  { "pcmpgtd", 2, 0x660f66, None, CpuSSE2,
2529    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2530    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2531      RegXMM } },
2532  { "pmaddwd", 2, 0xff5, None, CpuMMX,
2533    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2534    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2535      RegMMX } },
2536  { "pmaddwd", 2, 0x660ff5, None, CpuSSE2,
2537    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2538    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2539      RegXMM } },
2540  { "pmulhw", 2, 0xfe5, None, CpuMMX,
2541    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2542    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2543      RegMMX } },
2544  { "pmulhw", 2, 0x660fe5, None, CpuSSE2,
2545    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2546    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2547      RegXMM } },
2548  { "pmullw", 2, 0xfd5, None, CpuMMX,
2549    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2550    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2551      RegMMX } },
2552  { "pmullw", 2, 0x660fd5, None, CpuSSE2,
2553    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2554    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2555      RegXMM } },
2556  { "por", 2, 0xfeb, None, CpuMMX,
2557    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2558    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2559      RegMMX } },
2560  { "por", 2, 0x660feb, None, CpuSSE2,
2561    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2562    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2563      RegXMM } },
2564  { "psllw", 2, 0xff1, None, CpuMMX,
2565    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2566    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2567      RegMMX } },
2568  { "psllw", 2, 0x660ff1, None, CpuSSE2,
2569    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2570    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2571      RegXMM } },
2572  { "psllw", 2, 0xf71, 0x6, CpuMMX,
2573    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2574    { Imm8,
2575      RegMMX } },
2576  { "psllw", 2, 0x660f71, 0x6, CpuSSE2,
2577    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2578    { Imm8,
2579      RegXMM } },
2580  { "pslld", 2, 0xff2, None, CpuMMX,
2581    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2582    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2583      RegMMX } },
2584  { "pslld", 2, 0x660ff2, None, CpuSSE2,
2585    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2586    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2587      RegXMM } },
2588  { "pslld", 2, 0xf72, 0x6, CpuMMX,
2589    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2590    { Imm8,
2591      RegMMX } },
2592  { "pslld", 2, 0x660f72, 0x6, CpuSSE2,
2593    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2594    { Imm8,
2595      RegXMM } },
2596  { "psllq", 2, 0xff3, None, CpuMMX,
2597    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2598    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2599      RegMMX } },
2600  { "psllq", 2, 0x660ff3, None, CpuSSE2,
2601    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2602    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2603      RegXMM } },
2604  { "psllq", 2, 0xf73, 0x6, CpuMMX,
2605    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2606    { Imm8,
2607      RegMMX } },
2608  { "psllq", 2, 0x660f73, 0x6, CpuSSE2,
2609    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2610    { Imm8,
2611      RegXMM } },
2612  { "psraw", 2, 0xfe1, None, CpuMMX,
2613    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2614    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2615      RegMMX } },
2616  { "psraw", 2, 0x660fe1, None, CpuSSE2,
2617    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2618    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2619      RegXMM } },
2620  { "psraw", 2, 0xf71, 0x4, CpuMMX,
2621    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2622    { Imm8,
2623      RegMMX } },
2624  { "psraw", 2, 0x660f71, 0x4, CpuSSE2,
2625    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2626    { Imm8,
2627      RegXMM } },
2628  { "psrad", 2, 0xfe2, None, CpuMMX,
2629    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2630    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2631      RegMMX } },
2632  { "psrad", 2, 0x660fe2, None, CpuSSE2,
2633    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2634    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2635      RegXMM } },
2636  { "psrad", 2, 0xf72, 0x4, CpuMMX,
2637    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2638    { Imm8,
2639      RegMMX } },
2640  { "psrad", 2, 0x660f72, 0x4, CpuSSE2,
2641    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2642    { Imm8,
2643      RegXMM } },
2644  { "psrlw", 2, 0xfd1, None, CpuMMX,
2645    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2646    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2647      RegMMX } },
2648  { "psrlw", 2, 0x660fd1, None, CpuSSE2,
2649    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2650    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2651      RegXMM } },
2652  { "psrlw", 2, 0xf71, 0x2, CpuMMX,
2653    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2654    { Imm8,
2655      RegMMX } },
2656  { "psrlw", 2, 0x660f71, 0x2, CpuSSE2,
2657    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2658    { Imm8,
2659      RegXMM } },
2660  { "psrld", 2, 0xfd2, None, CpuMMX,
2661    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2662    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2663      RegMMX } },
2664  { "psrld", 2, 0x660fd2, None, CpuSSE2,
2665    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2666    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2667      RegXMM } },
2668  { "psrld", 2, 0xf72, 0x2, CpuMMX,
2669    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2670    { Imm8,
2671      RegMMX } },
2672  { "psrld", 2, 0x660f72, 0x2, CpuSSE2,
2673    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2674    { Imm8,
2675      RegXMM } },
2676  { "psrlq", 2, 0xfd3, None, CpuMMX,
2677    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2678    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2679      RegMMX } },
2680  { "psrlq", 2, 0x660fd3, None, CpuSSE2,
2681    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2682    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2683      RegXMM } },
2684  { "psrlq", 2, 0xf73, 0x2, CpuMMX,
2685    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2686    { Imm8,
2687      RegMMX } },
2688  { "psrlq", 2, 0x660f73, 0x2, CpuSSE2,
2689    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2690    { Imm8,
2691      RegXMM } },
2692  { "psubb", 2, 0xff8, None, CpuMMX,
2693    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2694    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2695      RegMMX } },
2696  { "psubb", 2, 0x660ff8, None, CpuSSE2,
2697    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2698    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2699      RegXMM } },
2700  { "psubw", 2, 0xff9, None, CpuMMX,
2701    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2702    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2703      RegMMX } },
2704  { "psubw", 2, 0x660ff9, None, CpuSSE2,
2705    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2706    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2707      RegXMM } },
2708  { "psubd", 2, 0xffa, None, CpuMMX,
2709    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2710    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2711      RegMMX } },
2712  { "psubd", 2, 0x660ffa, None, CpuSSE2,
2713    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2714    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2715      RegXMM } },
2716  { "psubq", 2, 0xffb, None, CpuSSE2,
2717    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2718    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2719      RegMMX } },
2720  { "psubq", 2, 0x660ffb, None, CpuSSE2,
2721    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2722    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2723      RegXMM } },
2724  { "psubsb", 2, 0xfe8, None, CpuMMX,
2725    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2726    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2727      RegMMX } },
2728  { "psubsb", 2, 0x660fe8, None, CpuSSE2,
2729    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2730    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2731      RegXMM } },
2732  { "psubsw", 2, 0xfe9, None, CpuMMX,
2733    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2734    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2735      RegMMX } },
2736  { "psubsw", 2, 0x660fe9, None, CpuSSE2,
2737    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2738    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2739      RegXMM } },
2740  { "psubusb", 2, 0xfd8, None, CpuMMX,
2741    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2742    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2743      RegMMX } },
2744  { "psubusb", 2, 0x660fd8, None, CpuSSE2,
2745    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2746    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2747      RegXMM } },
2748  { "psubusw", 2, 0xfd9, None, CpuMMX,
2749    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2750    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2751      RegMMX } },
2752  { "psubusw", 2, 0x660fd9, None, CpuSSE2,
2753    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2754    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2755      RegXMM } },
2756  { "punpckhbw", 2, 0xf68, None, CpuMMX,
2757    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2758    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2759      RegMMX } },
2760  { "punpckhbw", 2, 0x660f68, None, CpuSSE2,
2761    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2762    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2763      RegXMM } },
2764  { "punpckhwd", 2, 0xf69, None, CpuMMX,
2765    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2766    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2767      RegMMX } },
2768  { "punpckhwd", 2, 0x660f69, None, CpuSSE2,
2769    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2770    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2771      RegXMM } },
2772  { "punpckhdq", 2, 0xf6a, None, CpuMMX,
2773    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2774    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2775      RegMMX } },
2776  { "punpckhdq", 2, 0x660f6a, None, CpuSSE2,
2777    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2778    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2779      RegXMM } },
2780  { "punpcklbw", 2, 0xf60, None, CpuMMX,
2781    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2782    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2783      RegMMX } },
2784  { "punpcklbw", 2, 0x660f60, None, CpuSSE2,
2785    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2786    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2787      RegXMM } },
2788  { "punpcklwd", 2, 0xf61, None, CpuMMX,
2789    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2790    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2791      RegMMX } },
2792  { "punpcklwd", 2, 0x660f61, None, CpuSSE2,
2793    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2794    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2795      RegXMM } },
2796  { "punpckldq", 2, 0xf62, None, CpuMMX,
2797    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2798    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2799      RegMMX } },
2800  { "punpckldq", 2, 0x660f62, None, CpuSSE2,
2801    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2802    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2803      RegXMM } },
2804  { "pxor", 2, 0xfef, None, CpuMMX,
2805    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2806    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2807      RegMMX } },
2808  { "pxor", 2, 0x660fef, None, CpuSSE2,
2809    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2810    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2811      RegXMM } },
2812  { "addps", 2, 0xf58, None, CpuSSE,
2813    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2814    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2815      RegXMM } },
2816  { "addss", 2, 0xf30f58, None, CpuSSE,
2817    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2818    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2819      RegXMM } },
2820  { "andnps", 2, 0xf55, None, CpuSSE,
2821    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2822    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2823      RegXMM } },
2824  { "andps", 2, 0xf54, None, CpuSSE,
2825    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2826    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2827      RegXMM } },
2828  { "cmpeqps", 2, 0xfc2, 0x0, CpuSSE,
2829    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2830    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2831      RegXMM } },
2832  { "cmpeqss", 2, 0xf30fc2, 0x0, CpuSSE,
2833    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2834    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2835      RegXMM } },
2836  { "cmpleps", 2, 0xfc2, 0x2, CpuSSE,
2837    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2838    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2839      RegXMM } },
2840  { "cmpless", 2, 0xf30fc2, 0x2, CpuSSE,
2841    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2842    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2843      RegXMM } },
2844  { "cmpltps", 2, 0xfc2, 0x1, CpuSSE,
2845    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2846    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2847      RegXMM } },
2848  { "cmpltss", 2, 0xf30fc2, 0x1, CpuSSE,
2849    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2850    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2851      RegXMM } },
2852  { "cmpneqps", 2, 0xfc2, 0x4, CpuSSE,
2853    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2854    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2855      RegXMM } },
2856  { "cmpneqss", 2, 0xf30fc2, 0x4, CpuSSE,
2857    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2858    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2859      RegXMM } },
2860  { "cmpnleps", 2, 0xfc2, 0x6, CpuSSE,
2861    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2862    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2863      RegXMM } },
2864  { "cmpnless", 2, 0xf30fc2, 0x6, CpuSSE,
2865    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2866    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2867      RegXMM } },
2868  { "cmpnltps", 2, 0xfc2, 0x5, CpuSSE,
2869    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2870    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2871      RegXMM } },
2872  { "cmpnltss", 2, 0xf30fc2, 0x5, CpuSSE,
2873    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2874    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2875      RegXMM } },
2876  { "cmpordps", 2, 0xfc2, 0x7, CpuSSE,
2877    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2878    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2879      RegXMM } },
2880  { "cmpordss", 2, 0xf30fc2, 0x7, CpuSSE,
2881    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2882    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2883      RegXMM } },
2884  { "cmpunordps", 2, 0xfc2, 0x3, CpuSSE,
2885    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2886    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2887      RegXMM } },
2888  { "cmpunordss", 2, 0xf30fc2, 0x3, CpuSSE,
2889    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2890    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2891      RegXMM } },
2892  { "cmpps", 3, 0xfc2, None, CpuSSE,
2893    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2894    { Imm8,
2895      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2896      RegXMM } },
2897  { "cmpss", 3, 0xf30fc2, None, CpuSSE,
2898    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2899    { Imm8,
2900      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2901      RegXMM } },
2902  { "comiss", 2, 0xf2f, None, CpuSSE,
2903    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2904    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2905      RegXMM } },
2906  { "cvtpi2ps", 2, 0xf2a, None, CpuSSE,
2907    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2908    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2909      RegXMM } },
2910  { "cvtps2pi", 2, 0xf2d, None, CpuSSE,
2911    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2912    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2913      RegMMX } },
2914  { "cvtsi2ss", 2, 0xf30f2a, None, CpuSSE,
2915    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2916    { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2917      RegXMM } },
2918  { "cvtss2si", 2, 0xf30f2d, None, CpuSSE,
2919    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2920    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2921      Reg32|Reg64 } },
2922  { "cvttps2pi", 2, 0xf2c, None, CpuSSE,
2923    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2924    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2925      RegMMX } },
2926  { "cvttss2si", 2, 0xf30f2c, None, CpuSSE,
2927    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2928    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2929      Reg32|Reg64 } },
2930  { "divps", 2, 0xf5e, None, CpuSSE,
2931    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2932    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2933      RegXMM } },
2934  { "divss", 2, 0xf30f5e, None, CpuSSE,
2935    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2936    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2937      RegXMM } },
2938  { "ldmxcsr", 1, 0xfae, 0x2, CpuSSE,
2939    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2940    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2941  { "maskmovq", 2, 0xff7, None, CpuMMX2,
2942    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2943    { RegMMX,
2944      RegMMX } },
2945  { "maxps", 2, 0xf5f, None, CpuSSE,
2946    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2947    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2948      RegXMM } },
2949  { "maxss", 2, 0xf30f5f, None, CpuSSE,
2950    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2951    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2952      RegXMM } },
2953  { "minps", 2, 0xf5d, None, CpuSSE,
2954    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2955    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2956      RegXMM } },
2957  { "minss", 2, 0xf30f5d, None, CpuSSE,
2958    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2959    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2960      RegXMM } },
2961  { "movaps", 2, 0xf28, None, CpuSSE,
2962    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2963    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2964      RegXMM } },
2965  { "movaps", 2, 0xf29, None, CpuSSE,
2966    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2967    { RegXMM,
2968      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
2969  { "movhlps", 2, 0xf12, None, CpuSSE,
2970    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2971    { RegXMM,
2972      RegXMM } },
2973  { "movhps", 2, 0xf16, None, CpuSSE,
2974    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2975    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2976      RegXMM } },
2977  { "movhps", 2, 0xf17, None, CpuSSE,
2978    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2979    { RegXMM,
2980      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2981  { "movlhps", 2, 0xf16, None, CpuSSE,
2982    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2983    { RegXMM,
2984      RegXMM } },
2985  { "movlps", 2, 0xf12, None, CpuSSE,
2986    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2987    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2988      RegXMM } },
2989  { "movlps", 2, 0xf13, None, CpuSSE,
2990    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2991    { RegXMM,
2992      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2993  { "movmskps", 2, 0xf50, None, CpuSSE,
2994    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2995    { RegXMM,
2996      Reg32|Reg64 } },
2997  { "movntps", 2, 0xf2b, None, CpuSSE,
2998    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2999    { RegXMM,
3000      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3001  { "movntq", 2, 0xfe7, None, CpuMMX2,
3002    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3003    { RegMMX,
3004      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3005  { "movntdq", 2, 0x660fe7, None, CpuSSE2,
3006    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3007    { RegXMM,
3008      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3009  { "movss", 2, 0xf30f10, None, CpuSSE,
3010    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3011    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3012      RegXMM } },
3013  { "movss", 2, 0xf30f11, None, CpuSSE,
3014    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3015    { RegXMM,
3016      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3017  { "movups", 2, 0xf10, None, CpuSSE,
3018    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3019    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3020      RegXMM } },
3021  { "movups", 2, 0xf11, None, CpuSSE,
3022    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3023    { RegXMM,
3024      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3025  { "mulps", 2, 0xf59, None, CpuSSE,
3026    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3027    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3028      RegXMM } },
3029  { "mulss", 2, 0xf30f59, None, CpuSSE,
3030    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3031    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3032      RegXMM } },
3033  { "orps", 2, 0xf56, None, CpuSSE,
3034    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3035    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3036      RegXMM } },
3037  { "pavgb", 2, 0xfe0, None, CpuMMX2,
3038    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3039    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3040      RegMMX } },
3041  { "pavgb", 2, 0x660fe0, None, CpuSSE2,
3042    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3043    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3044      RegXMM } },
3045  { "pavgw", 2, 0xfe3, None, CpuMMX2,
3046    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3047    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3048      RegMMX } },
3049  { "pavgw", 2, 0x660fe3, None, CpuSSE2,
3050    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3051    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3052      RegXMM } },
3053  { "pextrw", 3, 0xfc5, None, CpuMMX2,
3054    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3055    { Imm8,
3056      RegMMX,
3057      Reg32|Reg64 } },
3058  { "pextrw", 3, 0x660fc5, None, CpuSSE2,
3059    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3060    { Imm8,
3061      RegXMM,
3062      Reg32|Reg64 } },
3063  { "pextrw", 3, 0x660f3a15, None, CpuSSE4_1,
3064    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3065    { Imm8,
3066      RegXMM,
3067      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3068  { "pinsrw", 3, 0xfc4, None, CpuMMX2,
3069    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3070    { Imm8,
3071      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3072      RegMMX } },
3073  { "pinsrw", 3, 0x660fc4, None, CpuSSE2,
3074    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3075    { Imm8,
3076      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3077      RegXMM } },
3078  { "pmaxsw", 2, 0xfee, None, CpuMMX2,
3079    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3080    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3081      RegMMX } },
3082  { "pmaxsw", 2, 0x660fee, None, CpuSSE2,
3083    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3084    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3085      RegXMM } },
3086  { "pmaxub", 2, 0xfde, None, CpuMMX2,
3087    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3088    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3089      RegMMX } },
3090  { "pmaxub", 2, 0x660fde, None, CpuSSE2,
3091    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3092    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3093      RegXMM } },
3094  { "pminsw", 2, 0xfea, None, CpuMMX2,
3095    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3096    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3097      RegMMX } },
3098  { "pminsw", 2, 0x660fea, None, CpuSSE2,
3099    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3100    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3101      RegXMM } },
3102  { "pminub", 2, 0xfda, None, CpuMMX2,
3103    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3104    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3105      RegMMX } },
3106  { "pminub", 2, 0x660fda, None, CpuSSE2,
3107    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3108    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3109      RegXMM } },
3110  { "pmovmskb", 2, 0xfd7, None, CpuMMX2,
3111    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3112    { RegMMX,
3113      Reg32|Reg64 } },
3114  { "pmovmskb", 2, 0x660fd7, None, CpuSSE2,
3115    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3116    { RegXMM,
3117      Reg32|Reg64 } },
3118  { "pmulhuw", 2, 0xfe4, None, CpuMMX2,
3119    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3120    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3121      RegMMX } },
3122  { "pmulhuw", 2, 0x660fe4, None, CpuSSE2,
3123    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3124    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3125      RegXMM } },
3126  { "prefetchnta", 1, 0xf18, 0x0, CpuMMX2,
3127    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3128    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3129  { "prefetcht0", 1, 0xf18, 0x1, CpuMMX2,
3130    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3131    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3132  { "prefetcht1", 1, 0xf18, 0x2, CpuMMX2,
3133    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3134    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3135  { "prefetcht2", 1, 0xf18, 0x3, CpuMMX2,
3136    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3137    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3138  { "psadbw", 2, 0xff6, None, CpuMMX2,
3139    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3140    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3141      RegMMX } },
3142  { "psadbw", 2, 0x660ff6, None, CpuSSE2,
3143    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3144    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3145      RegXMM } },
3146  { "pshufw", 3, 0xf70, None, CpuMMX2,
3147    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3148    { Imm8,
3149      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3150      RegMMX } },
3151  { "rcpps", 2, 0xf53, None, CpuSSE,
3152    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3153    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3154      RegXMM } },
3155  { "rcpss", 2, 0xf30f53, None, CpuSSE,
3156    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3157    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3158      RegXMM } },
3159  { "rsqrtps", 2, 0xf52, None, CpuSSE,
3160    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3161    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3162      RegXMM } },
3163  { "rsqrtss", 2, 0xf30f52, None, CpuSSE,
3164    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3165    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3166      RegXMM } },
3167  { "sfence", 0, 0xfae, 0xf8, CpuMMX2,
3168    IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3169    { 0 } },
3170  { "shufps", 3, 0xfc6, None, CpuSSE,
3171    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3172    { Imm8,
3173      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3174      RegXMM } },
3175  { "sqrtps", 2, 0xf51, None, CpuSSE,
3176    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3177    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3178      RegXMM } },
3179  { "sqrtss", 2, 0xf30f51, None, CpuSSE,
3180    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3181    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3182      RegXMM } },
3183  { "stmxcsr", 1, 0xfae, 0x3, CpuSSE,
3184    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3185    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3186  { "subps", 2, 0xf5c, None, CpuSSE,
3187    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3188    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3189      RegXMM } },
3190  { "subss", 2, 0xf30f5c, None, CpuSSE,
3191    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3192    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3193      RegXMM } },
3194  { "ucomiss", 2, 0xf2e, None, CpuSSE,
3195    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3196    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3197      RegXMM } },
3198  { "unpckhps", 2, 0xf15, None, CpuSSE,
3199    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3200    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3201      RegXMM } },
3202  { "unpcklps", 2, 0xf14, None, CpuSSE,
3203    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3204    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3205      RegXMM } },
3206  { "xorps", 2, 0xf57, None, CpuSSE,
3207    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3208    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3209      RegXMM } },
3210  { "addpd", 2, 0x660f58, None, CpuSSE2,
3211    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3212    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3213      RegXMM } },
3214  { "addsd", 2, 0xf20f58, None, CpuSSE2,
3215    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3216    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3217      RegXMM } },
3218  { "andnpd", 2, 0x660f55, None, CpuSSE2,
3219    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3220    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3221      RegXMM } },
3222  { "andpd", 2, 0x660f54, None, CpuSSE2,
3223    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3224    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3225      RegXMM } },
3226  { "cmpeqpd", 2, 0x660fc2, 0x0, CpuSSE2,
3227    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3228    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3229      RegXMM } },
3230  { "cmpeqsd", 2, 0xf20fc2, 0x0, CpuSSE2,
3231    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3232    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3233      RegXMM } },
3234  { "cmplepd", 2, 0x660fc2, 0x2, CpuSSE2,
3235    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3236    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3237      RegXMM } },
3238  { "cmplesd", 2, 0xf20fc2, 0x2, CpuSSE2,
3239    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3240    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3241      RegXMM } },
3242  { "cmpltpd", 2, 0x660fc2, 0x1, CpuSSE2,
3243    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3244    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3245      RegXMM } },
3246  { "cmpltsd", 2, 0xf20fc2, 0x1, CpuSSE2,
3247    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3248    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3249      RegXMM } },
3250  { "cmpneqpd", 2, 0x660fc2, 0x4, CpuSSE2,
3251    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3252    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3253      RegXMM } },
3254  { "cmpneqsd", 2, 0xf20fc2, 0x4, CpuSSE2,
3255    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3256    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3257      RegXMM } },
3258  { "cmpnlepd", 2, 0x660fc2, 0x6, CpuSSE2,
3259    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3260    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3261      RegXMM } },
3262  { "cmpnlesd", 2, 0xf20fc2, 0x6, CpuSSE2,
3263    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3264    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3265      RegXMM } },
3266  { "cmpnltpd", 2, 0x660fc2, 0x5, CpuSSE2,
3267    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3268    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3269      RegXMM } },
3270  { "cmpnltsd", 2, 0xf20fc2, 0x5, CpuSSE2,
3271    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3272    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3273      RegXMM } },
3274  { "cmpordpd", 2, 0x660fc2, 0x7, CpuSSE2,
3275    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3276    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3277      RegXMM } },
3278  { "cmpordsd", 2, 0xf20fc2, 0x7, CpuSSE2,
3279    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3280    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3281      RegXMM } },
3282  { "cmpunordpd", 2, 0x660fc2, 0x3, CpuSSE2,
3283    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3284    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3285      RegXMM } },
3286  { "cmpunordsd", 2, 0xf20fc2, 0x3, CpuSSE2,
3287    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3288    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3289      RegXMM } },
3290  { "cmppd", 3, 0x660fc2, None, CpuSSE2,
3291    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3292    { Imm8,
3293      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3294      RegXMM } },
3295  { "cmpsd", 0, 0xa7, None, 0,
3296    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3297    { 0 } },
3298  { "cmpsd", 2, 0xa7, None, 0,
3299    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3300    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3301      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
3302  { "cmpsd", 3, 0xf20fc2, None, CpuSSE2,
3303    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3304    { Imm8,
3305      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3306      RegXMM } },
3307  { "comisd", 2, 0x660f2f, None, CpuSSE2,
3308    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3309    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3310      RegXMM } },
3311  { "cvtpi2pd", 2, 0x660f2a, None, CpuSSE2,
3312    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3313    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3314      RegXMM } },
3315  { "cvtsi2sd", 2, 0xf20f2a, None, CpuSSE2,
3316    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3317    { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3318      RegXMM } },
3319  { "divpd", 2, 0x660f5e, None, CpuSSE2,
3320    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3321    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3322      RegXMM } },
3323  { "divsd", 2, 0xf20f5e, None, CpuSSE2,
3324    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3325    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3326      RegXMM } },
3327  { "maxpd", 2, 0x660f5f, None, CpuSSE2,
3328    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3329    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3330      RegXMM } },
3331  { "maxsd", 2, 0xf20f5f, None, CpuSSE2,
3332    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3333    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3334      RegXMM } },
3335  { "minpd", 2, 0x660f5d, None, CpuSSE2,
3336    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3337    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3338      RegXMM } },
3339  { "minsd", 2, 0xf20f5d, None, CpuSSE2,
3340    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3341    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3342      RegXMM } },
3343  { "movapd", 2, 0x660f28, None, CpuSSE2,
3344    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3345    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3346      RegXMM } },
3347  { "movapd", 2, 0x660f29, None, CpuSSE2,
3348    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3349    { RegXMM,
3350      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3351  { "movhpd", 2, 0x660f16, None, CpuSSE2,
3352    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3353    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3354      RegXMM } },
3355  { "movhpd", 2, 0x660f17, None, CpuSSE2,
3356    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3357    { RegXMM,
3358      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3359  { "movlpd", 2, 0x660f12, None, CpuSSE2,
3360    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3361    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3362      RegXMM } },
3363  { "movlpd", 2, 0x660f13, None, CpuSSE2,
3364    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3365    { RegXMM,
3366      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3367  { "movmskpd", 2, 0x660f50, None, CpuSSE2,
3368    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3369    { RegXMM,
3370      Reg32|Reg64 } },
3371  { "movntpd", 2, 0x660f2b, None, CpuSSE2,
3372    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3373    { RegXMM,
3374      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3375  { "movsd", 0, 0xa5, None, 0,
3376    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3377    { 0 } },
3378  { "movsd", 2, 0xa5, None, 0,
3379    Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3380    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3381      BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
3382  { "movsd", 2, 0xf20f10, None, CpuSSE2,
3383    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3384    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3385      RegXMM } },
3386  { "movsd", 2, 0xf20f11, None, CpuSSE2,
3387    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3388    { RegXMM,
3389      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3390  { "movupd", 2, 0x660f10, None, CpuSSE2,
3391    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3392    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3393      RegXMM } },
3394  { "movupd", 2, 0x660f11, None, CpuSSE2,
3395    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3396    { RegXMM,
3397      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3398  { "mulpd", 2, 0x660f59, None, CpuSSE2,
3399    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3400    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3401      RegXMM } },
3402  { "mulsd", 2, 0xf20f59, None, CpuSSE2,
3403    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3404    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3405      RegXMM } },
3406  { "orpd", 2, 0x660f56, None, CpuSSE2,
3407    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3408    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3409      RegXMM } },
3410  { "shufpd", 3, 0x660fc6, None, CpuSSE2,
3411    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3412    { Imm8,
3413      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3414      RegXMM } },
3415  { "sqrtpd", 2, 0x660f51, None, CpuSSE2,
3416    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3417    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3418      RegXMM } },
3419  { "sqrtsd", 2, 0xf20f51, None, CpuSSE2,
3420    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3421    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3422      RegXMM } },
3423  { "subpd", 2, 0x660f5c, None, CpuSSE2,
3424    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3425    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3426      RegXMM } },
3427  { "subsd", 2, 0xf20f5c, None, CpuSSE2,
3428    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3429    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3430      RegXMM } },
3431  { "ucomisd", 2, 0x660f2e, None, CpuSSE2,
3432    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3433    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3434      RegXMM } },
3435  { "unpckhpd", 2, 0x660f15, None, CpuSSE2,
3436    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3437    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3438      RegXMM } },
3439  { "unpcklpd", 2, 0x660f14, None, CpuSSE2,
3440    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3441    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3442      RegXMM } },
3443  { "xorpd", 2, 0x660f57, None, CpuSSE2,
3444    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3445    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3446      RegXMM } },
3447  { "cvtdq2pd", 2, 0xf30fe6, None, CpuSSE2,
3448    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3449    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3450      RegXMM } },
3451  { "cvtpd2dq", 2, 0xf20fe6, None, CpuSSE2,
3452    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3453    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3454      RegXMM } },
3455  { "cvtdq2ps", 2, 0xf5b, None, CpuSSE2,
3456    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3457    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3458      RegXMM } },
3459  { "cvtpd2pi", 2, 0x660f2d, None, CpuSSE2,
3460    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3461    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3462      RegMMX } },
3463  { "cvtpd2ps", 2, 0x660f5a, None, CpuSSE2,
3464    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3465    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3466      RegXMM } },
3467  { "cvtps2pd", 2, 0xf5a, None, CpuSSE2,
3468    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3469    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3470      RegXMM } },
3471  { "cvtps2dq", 2, 0x660f5b, None, CpuSSE2,
3472    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3473    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3474      RegXMM } },
3475  { "cvtsd2si", 2, 0xf20f2d, None, CpuSSE2,
3476    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3477    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3478      Reg32|Reg64 } },
3479  { "cvtsd2ss", 2, 0xf20f5a, None, CpuSSE2,
3480    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3481    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3482      RegXMM } },
3483  { "cvtss2sd", 2, 0xf30f5a, None, CpuSSE2,
3484    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3485    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3486      RegXMM } },
3487  { "cvttpd2pi", 2, 0x660f2c, None, CpuSSE2,
3488    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3489    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3490      RegMMX } },
3491  { "cvttsd2si", 2, 0xf20f2c, None, CpuSSE2,
3492    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3493    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3494      Reg32|Reg64 } },
3495  { "cvttpd2dq", 2, 0x660fe6, None, CpuSSE2,
3496    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3497    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3498      RegXMM } },
3499  { "cvttps2dq", 2, 0xf30f5b, None, CpuSSE2,
3500    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3501    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3502      RegXMM } },
3503  { "maskmovdqu", 2, 0x660ff7, None, CpuSSE2,
3504    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3505    { RegXMM,
3506      RegXMM } },
3507  { "movdqa", 2, 0x660f6f, None, CpuSSE2,
3508    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3509    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3510      RegXMM } },
3511  { "movdqa", 2, 0x660f7f, None, CpuSSE2,
3512    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3513    { RegXMM,
3514      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3515  { "movdqu", 2, 0xf30f6f, None, CpuSSE2,
3516    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3517    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3518      RegXMM } },
3519  { "movdqu", 2, 0xf30f7f, None, CpuSSE2,
3520    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3521    { RegXMM,
3522      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3523  { "movdq2q", 2, 0xf20fd6, None, CpuSSE2,
3524    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3525    { RegXMM,
3526      RegMMX } },
3527  { "movq2dq", 2, 0xf30fd6, None, CpuSSE2,
3528    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3529    { RegMMX,
3530      RegXMM } },
3531  { "pmuludq", 2, 0xff4, None, CpuSSE2,
3532    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3533    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3534      RegMMX } },
3535  { "pmuludq", 2, 0x660ff4, None, CpuSSE2,
3536    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3537    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3538      RegXMM } },
3539  { "pshufd", 3, 0x660f70, None, CpuSSE2,
3540    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3541    { Imm8,
3542      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3543      RegXMM } },
3544  { "pshufhw", 3, 0xf30f70, None, CpuSSE2,
3545    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3546    { Imm8,
3547      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3548      RegXMM } },
3549  { "pshuflw", 3, 0xf20f70, None, CpuSSE2,
3550    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3551    { Imm8,
3552      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3553      RegXMM } },
3554  { "pslldq", 2, 0x660f73, 0x7, CpuSSE2,
3555    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3556    { Imm8,
3557      RegXMM } },
3558  { "psrldq", 2, 0x660f73, 0x3, CpuSSE2,
3559    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3560    { Imm8,
3561      RegXMM } },
3562  { "punpckhqdq", 2, 0x660f6d, None, CpuSSE2,
3563    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3564    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3565      RegXMM } },
3566  { "punpcklqdq", 2, 0x660f6c, None, CpuSSE2,
3567    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3568    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3569      RegXMM } },
3570  { "addsubpd", 2, 0x660fd0, None, CpuSSE3,
3571    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3572    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3573      RegXMM } },
3574  { "addsubps", 2, 0xf20fd0, None, CpuSSE3,
3575    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3576    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3577      RegXMM } },
3578  { "cmpxchg16b", 1, 0xfc7, 0x1, CpuSSE3|Cpu64,
3579    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
3580    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3581  { "fisttp", 1, 0xdf, 0x1, CpuSSE3,
3582    Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
3583    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3584  { "fisttp", 1, 0xdd, 0x1, CpuSSE3,
3585    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3586    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3587  { "fisttpll", 1, 0xdd, 0x1, CpuSSE3,
3588    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3589    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3590  { "haddpd", 2, 0x660f7c, None, CpuSSE3,
3591    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3592    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3593      RegXMM } },
3594  { "haddps", 2, 0xf20f7c, None, CpuSSE3,
3595    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3596    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3597      RegXMM } },
3598  { "hsubpd", 2, 0x660f7d, None, CpuSSE3,
3599    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3600    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3601      RegXMM } },
3602  { "hsubps", 2, 0xf20f7d, None, CpuSSE3,
3603    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3604    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3605      RegXMM } },
3606  { "lddqu", 2, 0xf20ff0, None, CpuSSE3,
3607    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3608    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3609      RegXMM } },
3610  { "monitor", 0, 0xf01, 0xc8, CpuSSE3,
3611    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3612    { 0 } },
3613  { "monitor", 3, 0xf01, 0xc8, CpuSSE3|CpuNo64,
3614    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3615    { Reg16|Reg32,
3616      Reg32,
3617      Reg32 } },
3618  { "monitor", 3, 0xf01, 0xc8, CpuSSE3|Cpu64,
3619    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
3620    { Reg32|Reg64,
3621      Reg64,
3622      Reg64 } },
3623  { "movddup", 2, 0xf20f12, None, CpuSSE3,
3624    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3625    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3626      RegXMM } },
3627  { "movshdup", 2, 0xf30f16, None, CpuSSE3,
3628    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3629    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3630      RegXMM } },
3631  { "movsldup", 2, 0xf30f12, None, CpuSSE3,
3632    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3633    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3634      RegXMM } },
3635  { "mwait", 0, 0xf01, 0xc9, CpuSSE3,
3636    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3637    { 0 } },
3638  { "mwait", 2, 0xf01, 0xc9, CpuSSE3|CpuNo64,
3639    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3640    { Reg32,
3641      Reg32 } },
3642  { "mwait", 2, 0xf01, 0xc9, CpuSSE3|Cpu64,
3643    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
3644    { Reg64,
3645      Reg64 } },
3646  { "vmcall", 0, 0xf01, 0xc1, CpuVMX,
3647    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3648    { 0 } },
3649  { "vmclear", 1, 0x660fc7, 0x6, CpuVMX,
3650    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3651    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3652  { "vmlaunch", 0, 0xf01, 0xc2, CpuVMX,
3653    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3654    { 0 } },
3655  { "vmresume", 0, 0xf01, 0xc3, CpuVMX,
3656    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3657    { 0 } },
3658  { "vmptrld", 1, 0xfc7, 0x6, CpuVMX,
3659    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3660    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3661  { "vmptrst", 1, 0xfc7, 0x7, CpuVMX,
3662    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3663    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3664  { "vmread", 2, 0xf78, None, CpuVMX|CpuNo64,
3665    Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
3666    { Reg32,
3667      Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3668  { "vmread", 2, 0xf78, None, CpuVMX|Cpu64,
3669    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3670    { Reg64,
3671      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3672  { "vmwrite", 2, 0xf79, None, CpuVMX|CpuNo64,
3673    Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
3674    { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3675      Reg32 } },
3676  { "vmwrite", 2, 0xf79, None, CpuVMX|Cpu64,
3677    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3678    { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3679      Reg64 } },
3680  { "vmxoff", 0, 0xf01, 0xc4, CpuVMX,
3681    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3682    { 0 } },
3683  { "vmxon", 1, 0xf30fc7, 0x6, CpuVMX,
3684    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3685    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3686  { "phaddw", 2, 0xf3801, None, CpuSSSE3,
3687    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3688    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3689      RegMMX } },
3690  { "phaddw", 2, 0x660f3801, None, CpuSSSE3,
3691    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3692    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3693      RegXMM } },
3694  { "phaddd", 2, 0xf3802, None, CpuSSSE3,
3695    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3696    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3697      RegMMX } },
3698  { "phaddd", 2, 0x660f3802, None, CpuSSSE3,
3699    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3700    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3701      RegXMM } },
3702  { "phaddsw", 2, 0xf3803, None, CpuSSSE3,
3703    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3704    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3705      RegMMX } },
3706  { "phaddsw", 2, 0x660f3803, None, CpuSSSE3,
3707    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3708    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3709      RegXMM } },
3710  { "phsubw", 2, 0xf3805, None, CpuSSSE3,
3711    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3712    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3713      RegMMX } },
3714  { "phsubw", 2, 0x660f3805, None, CpuSSSE3,
3715    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3716    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3717      RegXMM } },
3718  { "phsubd", 2, 0xf3806, None, CpuSSSE3,
3719    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3720    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3721      RegMMX } },
3722  { "phsubd", 2, 0x660f3806, None, CpuSSSE3,
3723    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3724    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3725      RegXMM } },
3726  { "phsubsw", 2, 0xf3807, None, CpuSSSE3,
3727    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3728    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3729      RegMMX } },
3730  { "phsubsw", 2, 0x660f3807, None, CpuSSSE3,
3731    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3732    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3733      RegXMM } },
3734  { "pmaddubsw", 2, 0xf3804, None, CpuSSSE3,
3735    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3736    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3737      RegMMX } },
3738  { "pmaddubsw", 2, 0x660f3804, None, CpuSSSE3,
3739    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3740    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3741      RegXMM } },
3742  { "pmulhrsw", 2, 0xf380b, None, CpuSSSE3,
3743    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3744    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3745      RegMMX } },
3746  { "pmulhrsw", 2, 0x660f380b, None, CpuSSSE3,
3747    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3748    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3749      RegXMM } },
3750  { "pshufb", 2, 0xf3800, None, CpuSSSE3,
3751    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3752    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3753      RegMMX } },
3754  { "pshufb", 2, 0x660f3800, None, CpuSSSE3,
3755    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3756    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3757      RegXMM } },
3758  { "psignb", 2, 0xf3808, None, CpuSSSE3,
3759    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3760    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3761      RegMMX } },
3762  { "psignb", 2, 0x660f3808, None, CpuSSSE3,
3763    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3764    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3765      RegXMM } },
3766  { "psignw", 2, 0xf3809, None, CpuSSSE3,
3767    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3768    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3769      RegMMX } },
3770  { "psignw", 2, 0x660f3809, None, CpuSSSE3,
3771    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3772    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3773      RegXMM } },
3774  { "psignd", 2, 0xf380a, None, CpuSSSE3,
3775    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3776    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3777      RegMMX } },
3778  { "psignd", 2, 0x660f380a, None, CpuSSSE3,
3779    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3780    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3781      RegXMM } },
3782  { "palignr", 3, 0xf3a0f, None, CpuSSSE3,
3783    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3784    { Imm8,
3785      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3786      RegMMX } },
3787  { "palignr", 3, 0x660f3a0f, None, CpuSSSE3,
3788    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3789    { Imm8,
3790      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3791      RegXMM } },
3792  { "pabsb", 2, 0xf381c, None, CpuSSSE3,
3793    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3794    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3795      RegMMX } },
3796  { "pabsb", 2, 0x660f381c, None, CpuSSSE3,
3797    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3798    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3799      RegXMM } },
3800  { "pabsw", 2, 0xf381d, None, CpuSSSE3,
3801    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3802    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3803      RegMMX } },
3804  { "pabsw", 2, 0x660f381d, None, CpuSSSE3,
3805    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3806    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3807      RegXMM } },
3808  { "pabsd", 2, 0xf381e, None, CpuSSSE3,
3809    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3810    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3811      RegMMX } },
3812  { "pabsd", 2, 0x660f381e, None, CpuSSSE3,
3813    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3814    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3815      RegXMM } },
3816  { "blendpd", 3, 0x660f3a0d, None, CpuSSE4_1,
3817    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3818    { Imm8,
3819      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3820      RegXMM } },
3821  { "blendps", 3, 0x660f3a0c, None, CpuSSE4_1,
3822    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3823    { Imm8,
3824      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3825      RegXMM } },
3826  { "blendvpd", 3, 0x660f3815, None, CpuSSE4_1,
3827    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3828    { RegXMM,
3829      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3830      RegXMM } },
3831  { "blendvps", 3, 0x660f3814, None, CpuSSE4_1,
3832    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3833    { RegXMM,
3834      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3835      RegXMM } },
3836  { "dppd", 3, 0x660f3a41, None, CpuSSE4_1,
3837    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3838    { Imm8,
3839      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3840      RegXMM } },
3841  { "dpps", 3, 0x660f3a40, None, CpuSSE4_1,
3842    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3843    { Imm8,
3844      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3845      RegXMM } },
3846  { "extractps", 3, 0x660f3a17, None, CpuSSE4_1,
3847    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3848    { Imm8,
3849      RegXMM,
3850      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3851  { "insertps", 3, 0x660f3a21, None, CpuSSE4_1,
3852    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3853    { Imm8,
3854      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3855      RegXMM } },
3856  { "movntdqa", 2, 0x660f382a, None, CpuSSE4_1,
3857    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3858    { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3859      RegXMM } },
3860  { "mpsadbw", 3, 0x660f3a42, None, CpuSSE4_1,
3861    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3862    { Imm8,
3863      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3864      RegXMM } },
3865  { "packusdw", 2, 0x660f382b, None, CpuSSE4_1,
3866    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3867    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3868      RegXMM } },
3869  { "pblendvb", 3, 0x660f3810, None, CpuSSE4_1,
3870    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3871    { RegXMM,
3872      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3873      RegXMM } },
3874  { "pblendw", 3, 0x660f3a0e, None, CpuSSE4_1,
3875    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3876    { Imm8,
3877      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3878      RegXMM } },
3879  { "pcmpeqq", 2, 0x660f3829, None, CpuSSE4_1,
3880    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3881    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3882      RegXMM } },
3883  { "pextrb", 3, 0x660f3a14, None, CpuSSE4_1,
3884    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3885    { Imm8,
3886      RegXMM,
3887      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3888  { "pextrd", 3, 0x660f3a16, None, CpuSSE4_1,
3889    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3890    { Imm8,
3891      RegXMM,
3892      Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3893  { "pextrq", 3, 0x660f3a16, None, CpuSSE4_1|Cpu64,
3894    Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3895    { Imm8,
3896      RegXMM,
3897      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3898  { "phminposuw", 2, 0x660f3841, None, CpuSSE4_1,
3899    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3900    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3901      RegXMM } },
3902  { "pinsrb", 3, 0x660f3a20, None, CpuSSE4_1,
3903    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3904    { Imm8,
3905      Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3906      RegXMM } },
3907  { "pinsrd", 3, 0x660f3a22, None, CpuSSE4_1,
3908    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3909    { Imm8,
3910      Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3911      RegXMM } },
3912  { "pinsrq", 3, 0x660f3a22, None, CpuSSE4_1|Cpu64,
3913    Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3914    { Imm8,
3915      Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3916      RegXMM } },
3917  { "pmaxsb", 2, 0x660f383c, None, CpuSSE4_1,
3918    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3919    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3920      RegXMM } },
3921  { "pmaxsd", 2, 0x660f383d, None, CpuSSE4_1,
3922    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3923    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3924      RegXMM } },
3925  { "pmaxud", 2, 0x660f383f, None, CpuSSE4_1,
3926    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3927    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3928      RegXMM } },
3929  { "pmaxuw", 2, 0x660f383e, None, CpuSSE4_1,
3930    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3931    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3932      RegXMM } },
3933  { "pminsb", 2, 0x660f3838, None, CpuSSE4_1,
3934    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3935    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3936      RegXMM } },
3937  { "pminsd", 2, 0x660f3839, None, CpuSSE4_1,
3938    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3939    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3940      RegXMM } },
3941  { "pminud", 2, 0x660f383b, None, CpuSSE4_1,
3942    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3943    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3944      RegXMM } },
3945  { "pminuw", 2, 0x660f383a, None, CpuSSE4_1,
3946    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3947    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3948      RegXMM } },
3949  { "pmovsxbw", 2, 0x660f3820, None, CpuSSE4_1,
3950    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3951    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3952      RegXMM } },
3953  { "pmovsxbd", 2, 0x660f3821, None, CpuSSE4_1,
3954    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3955    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3956      RegXMM } },
3957  { "pmovsxbq", 2, 0x660f3822, None, CpuSSE4_1,
3958    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3959    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3960      RegXMM } },
3961  { "pmovsxwd", 2, 0x660f3823, None, CpuSSE4_1,
3962    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3963    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3964      RegXMM } },
3965  { "pmovsxwq", 2, 0x660f3824, None, CpuSSE4_1,
3966    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3967    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3968      RegXMM } },
3969  { "pmovsxdq", 2, 0x660f3825, None, CpuSSE4_1,
3970    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3971    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3972      RegXMM } },
3973  { "pmovzxbw", 2, 0x660f3830, None, CpuSSE4_1,
3974    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3975    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3976      RegXMM } },
3977  { "pmovzxbd", 2, 0x660f3831, None, CpuSSE4_1,
3978    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3979    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3980      RegXMM } },
3981  { "pmovzxbq", 2, 0x660f3832, None, CpuSSE4_1,
3982    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3983    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3984      RegXMM } },
3985  { "pmovzxwd", 2, 0x660f3833, None, CpuSSE4_1,
3986    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3987    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3988      RegXMM } },
3989  { "pmovzxwq", 2, 0x660f3834, None, CpuSSE4_1,
3990    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3991    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3992      RegXMM } },
3993  { "pmovzxdq", 2, 0x660f3835, None, CpuSSE4_1,
3994    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3995    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3996      RegXMM } },
3997  { "pmuldq", 2, 0x660f3828, None, CpuSSE4_1,
3998    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3999    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4000      RegXMM } },
4001  { "pmulld", 2, 0x660f3840, None, CpuSSE4_1,
4002    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4003    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4004      RegXMM } },
4005  { "ptest", 2, 0x660f3817, None, CpuSSE4_1,
4006    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4007    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4008      RegXMM } },
4009  { "roundpd", 3, 0x660f3a09, None, CpuSSE4_1,
4010    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4011    { Imm8,
4012      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4013      RegXMM } },
4014  { "roundps", 3, 0x660f3a08, None, CpuSSE4_1,
4015    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4016    { Imm8,
4017      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4018      RegXMM } },
4019  { "roundsd", 3, 0x660f3a0b, None, CpuSSE4_1,
4020    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
4021    { Imm8,
4022      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4023      RegXMM } },
4024  { "roundss", 3, 0x660f3a0a, None, CpuSSE4_1,
4025    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4026    { Imm8,
4027      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4028      RegXMM } },
4029  { "pcmpgtq", 2, 0x660f3837, None, CpuSSE4_2,
4030    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4031    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4032      RegXMM } },
4033  { "pcmpestri", 3, 0x660f3a61, None, CpuSSE4_2,
4034    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4035    { Imm8,
4036      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4037      RegXMM } },
4038  { "pcmpestrm", 3, 0x660f3a60, None, CpuSSE4_2,
4039    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4040    { Imm8,
4041      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4042      RegXMM } },
4043  { "pcmpistri", 3, 0x660f3a63, None, CpuSSE4_2,
4044    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4045    { Imm8,
4046      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4047      RegXMM } },
4048  { "pcmpistrm", 3, 0x660f3a62, None, CpuSSE4_2,
4049    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4050    { Imm8,
4051      BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4052      RegXMM } },
4053  { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2,
4054    Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
4055    { Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4056      Reg32 } },
4057  { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64,
4058    Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64,
4059    { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4060      Reg64 } },
4061  { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2,
4062    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4063    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4064      Reg32 } },
4065  { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64,
4066    Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
4067    { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4068      Reg64 } },
4069  { "prefetch", 1, 0xf0d, 0x0, Cpu3dnow,
4070    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4071    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4072  { "prefetchw", 1, 0xf0d, 0x1, Cpu3dnow,
4073    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4074    { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4075  { "femms", 0, 0xf0e, None, Cpu3dnow,
4076    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4077    { 0 } },
4078  { "pavgusb", 2, 0xf0f, 0xbf, Cpu3dnow,
4079    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4080    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4081      RegMMX } },
4082  { "pf2id", 2, 0xf0f, 0x1d, Cpu3dnow,
4083    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4084    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4085      RegMMX } },
4086  { "pf2iw", 2, 0xf0f, 0x1c, Cpu3dnowA,
4087    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4088    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4089      RegMMX } },
4090  { "pfacc", 2, 0xf0f, 0xae, Cpu3dnow,
4091    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4092    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4093      RegMMX } },
4094  { "pfadd", 2, 0xf0f, 0x9e, Cpu3dnow,
4095    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4096    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4097      RegMMX } },
4098  { "pfcmpeq", 2, 0xf0f, 0xb0, Cpu3dnow,
4099    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4100    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4101      RegMMX } },
4102  { "pfcmpge", 2, 0xf0f, 0x90, Cpu3dnow,
4103    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4104    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4105      RegMMX } },
4106  { "pfcmpgt", 2, 0xf0f, 0xa0, Cpu3dnow,
4107    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4108    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4109      RegMMX } },
4110  { "pfmax", 2, 0xf0f, 0xa4, Cpu3dnow,
4111    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4112    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4113      RegMMX } },
4114  { "pfmin", 2, 0xf0f, 0x94, Cpu3dnow,
4115    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4116    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4117      RegMMX } },
4118  { "pfmul", 2, 0xf0f, 0xb4, Cpu3dnow,
4119    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4120    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4121      RegMMX } },
4122  { "pfnacc", 2, 0xf0f, 0x8a, Cpu3dnowA,
4123    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4124    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4125      RegMMX } },
4126  { "pfpnacc", 2, 0xf0f, 0x8e, Cpu3dnowA,
4127    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4128    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4129      RegMMX } },
4130  { "pfrcp", 2, 0xf0f, 0x96, Cpu3dnow,
4131    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4132    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4133      RegMMX } },
4134  { "pfrcpit1", 2, 0xf0f, 0xa6, Cpu3dnow,
4135    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4136    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4137      RegMMX } },
4138  { "pfrcpit2", 2, 0xf0f, 0xb6, Cpu3dnow,
4139    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4140    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4141      RegMMX } },
4142  { "pfrsqit1", 2, 0xf0f, 0xa7, Cpu3dnow,
4143    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4144    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4145      RegMMX } },
4146  { "pfrsqrt", 2, 0xf0f, 0x97, Cpu3dnow,
4147    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4148    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4149      RegMMX } },
4150  { "pfsub", 2, 0xf0f, 0x9a, Cpu3dnow,
4151    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4152    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4153      RegMMX } },
4154  { "pfsubr", 2, 0xf0f, 0xaa, Cpu3dnow,
4155    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4156    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4157      RegMMX } },
4158  { "pi2fd", 2, 0xf0f, 0xd, Cpu3dnow,
4159    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4160    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4161      RegMMX } },
4162  { "pi2fw", 2, 0xf0f, 0xc, Cpu3dnowA,
4163    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4164    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4165      RegMMX } },
4166  { "pmulhrw", 2, 0xf0f, 0xb7, Cpu3dnow,
4167    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4168    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4169      RegMMX } },
4170  { "pswapd", 2, 0xf0f, 0xbb, Cpu3dnowA,
4171    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4172    { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4173      RegMMX } },
4174  { "syscall", 0, 0xf05, None, CpuK6,
4175    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4176    { 0 } },
4177  { "sysret", 0, 0xf07, None, CpuK6,
4178    DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
4179    { 0 } },
4180  { "swapgs", 0, 0xf01, 0xf8, Cpu64,
4181    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4182    { 0 } },
4183  { "rdtscp", 0, 0xf01, 0xf9, CpuSledgehammer,
4184    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4185    { 0 } },
4186  { "clgi", 0, 0xf01, 0xdd, CpuSVME,
4187    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4188    { 0 } },
4189  { "invlpga", 0, 0xf01, 0xdf, CpuSVME,
4190    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4191    { 0 } },
4192  { "invlpga", 2, 0xf01, 0xdf, CpuSVME,
4193    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
4194    { Reg32|Reg64,
4195      Reg32 } },
4196  { "skinit", 0, 0xf01, 0xde, CpuSVME,
4197    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4198    { 0 } },
4199  { "skinit", 1, 0xf01, 0xde, CpuSVME,
4200    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4201    { Reg32 } },
4202  { "stgi", 0, 0xf01, 0xdc, CpuSVME,
4203    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4204    { 0 } },
4205  { "vmload", 0, 0xf01, 0xda, CpuSVME,
4206    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4207    { 0 } },
4208  { "vmload", 1, 0xf01, 0xda, CpuSVME,
4209    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
4210    { Reg32|Reg64 } },
4211  { "vmmcall", 0, 0xf01, 0xd9, CpuSVME,
4212    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4213    { 0 } },
4214  { "vmrun", 0, 0xf01, 0xd8, CpuSVME,
4215    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4216    { 0 } },
4217  { "vmrun", 1, 0xf01, 0xd8, CpuSVME,
4218    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
4219    { Reg32|Reg64 } },
4220  { "vmsave", 0, 0xf01, 0xdb, CpuSVME,
4221    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4222    { 0 } },
4223  { "vmsave", 1, 0xf01, 0xdb, CpuSVME,
4224    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
4225    { Reg32|Reg64 } },
4226  { "movntsd", 2, 0xf20f2b, None, CpuSSE4a,
4227    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4228    { RegXMM,
4229      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4230  { "movntss", 2, 0xf30f2b, None, CpuSSE4a,
4231    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4232    { RegXMM,
4233      BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4234  { "extrq", 3, 0x660f78, 0x0, CpuSSE4a,
4235    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4236    { Imm8,
4237      Imm8,
4238      RegXMM } },
4239  { "extrq", 2, 0x660f79, None, CpuSSE4a,
4240    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4241    { RegXMM,
4242      RegXMM } },
4243  { "insertq", 2, 0xf20f79, None, CpuSSE4a,
4244    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4245    { RegXMM,
4246      RegXMM } },
4247  { "insertq", 4, 0xf20f78, None, CpuSSE4a,
4248    Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4249    { Imm8,
4250      Imm8,
4251      RegXMM,
4252      RegXMM } },
4253  { "popcnt", 2, 0xf30fb8, None, CpuABM|CpuSSE4_2,
4254    Modrm|No_bSuf|No_sSuf|No_xSuf,
4255    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4256      Reg16|Reg32|Reg64 } },
4257  { "lzcnt", 2, 0xf30fbd, None, CpuABM,
4258    Modrm|No_bSuf|No_sSuf|No_xSuf,
4259    { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4260      Reg16|Reg32|Reg64 } },
4261  { "xstore-rng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4262    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4263    { 0 } },
4264  { "xcrypt-ecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock,
4265    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4266    { 0 } },
4267  { "xcrypt-cbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock,
4268    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4269    { 0 } },
4270  { "xcrypt-ctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock,
4271    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4272    { 0 } },
4273  { "xcrypt-cfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock,
4274    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4275    { 0 } },
4276  { "xcrypt-ofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock,
4277    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4278    { 0 } },
4279  { "montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock,
4280    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4281    { 0 } },
4282  { "xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock,
4283    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4284    { 0 } },
4285  { "xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock,
4286    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4287    { 0 } },
4288  { "xstorerng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4289    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4290    { 0 } },
4291  { "xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock,
4292    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4293    { 0 } },
4294  { "xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock,
4295    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4296    { 0 } },
4297  { "xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock,
4298    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4299    { 0 } },
4300  { "xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock,
4301    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4302    { 0 } },
4303  { "xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock,
4304    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4305    { 0 } },
4306  { "xstore", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4307    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4308    { 0 } },
4309  { NULL, 0, 0, 0, 0, 0, { 0 } }
4310};
4311
4312/* i386 register table.  */
4313
4314const reg_entry i386_regtab[] =
4315{
4316  { "st", FloatReg|FloatAcc, 0, 0 },
4317  { "al", Reg8|Acc, 0, 0 },
4318  { "cl", Reg8|ShiftCount, 0, 1 },
4319  { "dl", Reg8, 0, 2 },
4320  { "bl", Reg8, 0, 3 },
4321  { "ah", Reg8, 0, 4 },
4322  { "ch", Reg8, 0, 5 },
4323  { "dh", Reg8, 0, 6 },
4324  { "bh", Reg8, 0, 7 },
4325  { "axl", Reg8|Acc, RegRex64, 0 },
4326  { "cxl", Reg8, RegRex64, 1 },
4327  { "dxl", Reg8, RegRex64, 2 },
4328  { "bxl", Reg8, RegRex64, 3 },
4329  { "spl", Reg8, RegRex64, 4 },
4330  { "bpl", Reg8, RegRex64, 5 },
4331  { "sil", Reg8, RegRex64, 6 },
4332  { "dil", Reg8, RegRex64, 7 },
4333  { "r8b", Reg8, RegRex|RegRex64, 0 },
4334  { "r9b", Reg8, RegRex|RegRex64, 1 },
4335  { "r10b", Reg8, RegRex|RegRex64, 2 },
4336  { "r11b", Reg8, RegRex|RegRex64, 3 },
4337  { "r12b", Reg8, RegRex|RegRex64, 4 },
4338  { "r13b", Reg8, RegRex|RegRex64, 5 },
4339  { "r14b", Reg8, RegRex|RegRex64, 6 },
4340  { "r15b", Reg8, RegRex|RegRex64, 7 },
4341  { "ax", Reg16|Acc, 0, 0 },
4342  { "cx", Reg16, 0, 1 },
4343  { "dx", Reg16|InOutPortReg, 0, 2 },
4344  { "bx", Reg16|BaseIndex, 0, 3 },
4345  { "sp", Reg16, 0, 4 },
4346  { "bp", Reg16|BaseIndex, 0, 5 },
4347  { "si", Reg16|BaseIndex, 0, 6 },
4348  { "di", Reg16|BaseIndex, 0, 7 },
4349  { "r8w", Reg16, RegRex, 0 },
4350  { "r9w", Reg16, RegRex, 1 },
4351  { "r10w", Reg16, RegRex, 2 },
4352  { "r11w", Reg16, RegRex, 3 },
4353  { "r12w", Reg16, RegRex, 4 },
4354  { "r13w", Reg16, RegRex, 5 },
4355  { "r14w", Reg16, RegRex, 6 },
4356  { "r15w", Reg16, RegRex, 7 },
4357  { "eax", Reg32|BaseIndex|Acc, 0, 0 },
4358  { "ecx", Reg32|BaseIndex, 0, 1 },
4359  { "edx", Reg32|BaseIndex, 0, 2 },
4360  { "ebx", Reg32|BaseIndex, 0, 3 },
4361  { "esp", Reg32, 0, 4 },
4362  { "ebp", Reg32|BaseIndex, 0, 5 },
4363  { "esi", Reg32|BaseIndex, 0, 6 },
4364  { "edi", Reg32|BaseIndex, 0, 7 },
4365  { "r8d", Reg32|BaseIndex, RegRex, 0 },
4366  { "r9d", Reg32|BaseIndex, RegRex, 1 },
4367  { "r10d", Reg32|BaseIndex, RegRex, 2 },
4368  { "r11d", Reg32|BaseIndex, RegRex, 3 },
4369  { "r12d", Reg32|BaseIndex, RegRex, 4 },
4370  { "r13d", Reg32|BaseIndex, RegRex, 5 },
4371  { "r14d", Reg32|BaseIndex, RegRex, 6 },
4372  { "r15d", Reg32|BaseIndex, RegRex, 7 },
4373  { "rax", Reg64|BaseIndex|Acc, 0, 0 },
4374  { "rcx", Reg64|BaseIndex, 0, 1 },
4375  { "rdx", Reg64|BaseIndex, 0, 2 },
4376  { "rbx", Reg64|BaseIndex, 0, 3 },
4377  { "rsp", Reg64, 0, 4 },
4378  { "rbp", Reg64|BaseIndex, 0, 5 },
4379  { "rsi", Reg64|BaseIndex, 0, 6 },
4380  { "rdi", Reg64|BaseIndex, 0, 7 },
4381  { "r8", Reg64|BaseIndex, RegRex, 0 },
4382  { "r9", Reg64|BaseIndex, RegRex, 1 },
4383  { "r10", Reg64|BaseIndex, RegRex, 2 },
4384  { "r11", Reg64|BaseIndex, RegRex, 3 },
4385  { "r12", Reg64|BaseIndex, RegRex, 4 },
4386  { "r13", Reg64|BaseIndex, RegRex, 5 },
4387  { "r14", Reg64|BaseIndex, RegRex, 6 },
4388  { "r15", Reg64|BaseIndex, RegRex, 7 },
4389  { "es", SReg2, 0, 0 },
4390  { "cs", SReg2, 0, 1 },
4391  { "ss", SReg2, 0, 2 },
4392  { "ds", SReg2, 0, 3 },
4393  { "fs", SReg3, 0, 4 },
4394  { "gs", SReg3, 0, 5 },
4395  { "cr0", Control, 0, 0 },
4396  { "cr1", Control, 0, 1 },
4397  { "cr2", Control, 0, 2 },
4398  { "cr3", Control, 0, 3 },
4399  { "cr4", Control, 0, 4 },
4400  { "cr5", Control, 0, 5 },
4401  { "cr6", Control, 0, 6 },
4402  { "cr7", Control, 0, 7 },
4403  { "cr8", Control, RegRex, 0 },
4404  { "cr9", Control, RegRex, 1 },
4405  { "cr10", Control, RegRex, 2 },
4406  { "cr11", Control, RegRex, 3 },
4407  { "cr12", Control, RegRex, 4 },
4408  { "cr13", Control, RegRex, 5 },
4409  { "cr14", Control, RegRex, 6 },
4410  { "cr15", Control, RegRex, 7 },
4411  { "db0", Debug, 0, 0 },
4412  { "db1", Debug, 0, 1 },
4413  { "db2", Debug, 0, 2 },
4414  { "db3", Debug, 0, 3 },
4415  { "db4", Debug, 0, 4 },
4416  { "db5", Debug, 0, 5 },
4417  { "db6", Debug, 0, 6 },
4418  { "db7", Debug, 0, 7 },
4419  { "db8", Debug, RegRex, 0 },
4420  { "db9", Debug, RegRex, 1 },
4421  { "db10", Debug, RegRex, 2 },
4422  { "db11", Debug, RegRex, 3 },
4423  { "db12", Debug, RegRex, 4 },
4424  { "db13", Debug, RegRex, 5 },
4425  { "db14", Debug, RegRex, 6 },
4426  { "db15", Debug, RegRex, 7 },
4427  { "dr0", Debug, 0, 0 },
4428  { "dr1", Debug, 0, 1 },
4429  { "dr2", Debug, 0, 2 },
4430  { "dr3", Debug, 0, 3 },
4431  { "dr4", Debug, 0, 4 },
4432  { "dr5", Debug, 0, 5 },
4433  { "dr6", Debug, 0, 6 },
4434  { "dr7", Debug, 0, 7 },
4435  { "dr8", Debug, RegRex, 0 },
4436  { "dr9", Debug, RegRex, 1 },
4437  { "dr10", Debug, RegRex, 2 },
4438  { "dr11", Debug, RegRex, 3 },
4439  { "dr12", Debug, RegRex, 4 },
4440  { "dr13", Debug, RegRex, 5 },
4441  { "dr14", Debug, RegRex, 6 },
4442  { "dr15", Debug, RegRex, 7 },
4443  { "tr0", Test, 0, 0 },
4444  { "tr1", Test, 0, 1 },
4445  { "tr2", Test, 0, 2 },
4446  { "tr3", Test, 0, 3 },
4447  { "tr4", Test, 0, 4 },
4448  { "tr5", Test, 0, 5 },
4449  { "tr6", Test, 0, 6 },
4450  { "tr7", Test, 0, 7 },
4451  { "mm0", RegMMX, 0, 0 },
4452  { "mm1", RegMMX, 0, 1 },
4453  { "mm2", RegMMX, 0, 2 },
4454  { "mm3", RegMMX, 0, 3 },
4455  { "mm4", RegMMX, 0, 4 },
4456  { "mm5", RegMMX, 0, 5 },
4457  { "mm6", RegMMX, 0, 6 },
4458  { "mm7", RegMMX, 0, 7 },
4459  { "xmm0", RegXMM, 0, 0 },
4460  { "xmm1", RegXMM, 0, 1 },
4461  { "xmm2", RegXMM, 0, 2 },
4462  { "xmm3", RegXMM, 0, 3 },
4463  { "xmm4", RegXMM, 0, 4 },
4464  { "xmm5", RegXMM, 0, 5 },
4465  { "xmm6", RegXMM, 0, 6 },
4466  { "xmm7", RegXMM, 0, 7 },
4467  { "xmm8", RegXMM, RegRex, 0 },
4468  { "xmm9", RegXMM, RegRex, 1 },
4469  { "xmm10", RegXMM, RegRex, 2 },
4470  { "xmm11", RegXMM, RegRex, 3 },
4471  { "xmm12", RegXMM, RegRex, 4 },
4472  { "xmm13", RegXMM, RegRex, 5 },
4473  { "xmm14", RegXMM, RegRex, 6 },
4474  { "xmm15", RegXMM, RegRex, 7 },
4475  { "rip", BaseIndex, 0, 0 },
4476  { "st(0)", FloatReg|FloatAcc, 0, 0 },
4477  { "st(1)", FloatReg, 0, 1 },
4478  { "st(2)", FloatReg, 0, 2 },
4479  { "st(3)", FloatReg, 0, 3 },
4480  { "st(4)", FloatReg, 0, 4 },
4481  { "st(5)", FloatReg, 0, 5 },
4482  { "st(6)", FloatReg, 0, 6 },
4483  { "st(7)", FloatReg, 0, 7 },
4484};
4485
4486const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);
4487