Searched refs:EBIU_SDBCTL (Results 1 - 25 of 26) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h453 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
454 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
H A DdefBF532.h177 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1000 /* EBIU_SDBCTL Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h453 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
454 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
H A DdefBF532.h177 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1000 /* EBIU_SDBCTL Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/kernel/
H A Dsetup.c767 #if defined(EBIU_SDBCTL)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/kernel/
H A Dsetup.c767 #if defined(EBIU_SDBCTL)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h371 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
372 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
H A DdefBF51x_base.h213 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1115 /* EBIU_SDBCTL Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h388 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
389 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
H A DdefBF52x_base.h212 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1124 /* EBIU_SDBCTL Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h371 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
372 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
H A DdefBF51x_base.h213 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1115 /* EBIU_SDBCTL Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h388 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
389 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
H A DdefBF52x_base.h212 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1124 /* EBIU_SDBCTL Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h191 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1485 /* EBIU_SDBCTL Masks */
H A DcdefBF534.h350 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
351 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h298 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1584 /* EBIU_SDBCTL Masks */
H A DcdefBF561.h503 #define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
504 #define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h191 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1485 /* EBIU_SDBCTL Masks */
H A DcdefBF534.h350 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
351 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h298 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
1584 /* EBIU_SDBCTL Masks */
H A DcdefBF561.h503 #define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
504 #define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h484 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
485 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
H A DdefBF539.h191 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
2217 /* EBIU_SDBCTL Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h484 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
485 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)

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