/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf533/include/mach/ |
H A D | cdefBF532.h | 453 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 454 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
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H A D | defBF532.h | 177 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1000 /* EBIU_SDBCTL Masks */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/ |
H A D | cdefBF532.h | 453 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 454 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
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H A D | defBF532.h | 177 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1000 /* EBIU_SDBCTL Masks */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/kernel/ |
H A D | setup.c | 767 #if defined(EBIU_SDBCTL)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/kernel/ |
H A D | setup.c | 767 #if defined(EBIU_SDBCTL)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/ |
H A D | cdefBF51x_base.h | 371 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 372 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
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H A D | defBF51x_base.h | 213 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1115 /* EBIU_SDBCTL Masks */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/ |
H A D | cdefBF52x_base.h | 388 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 389 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
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H A D | defBF52x_base.h | 212 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1124 /* EBIU_SDBCTL Masks */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/ |
H A D | cdefBF51x_base.h | 371 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 372 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
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H A D | defBF51x_base.h | 213 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1115 /* EBIU_SDBCTL Masks */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/ |
H A D | cdefBF52x_base.h | 388 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 389 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
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H A D | defBF52x_base.h | 212 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1124 /* EBIU_SDBCTL Masks */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/ |
H A D | defBF534.h | 191 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1485 /* EBIU_SDBCTL Masks */
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H A D | cdefBF534.h | 350 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 351 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf561/include/mach/ |
H A D | defBF561.h | 298 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1584 /* EBIU_SDBCTL Masks */
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H A D | cdefBF561.h | 503 #define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL) 504 #define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/ |
H A D | defBF534.h | 191 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1485 /* EBIU_SDBCTL Masks */
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H A D | cdefBF534.h | 350 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 351 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/ |
H A D | defBF561.h | 298 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 1584 /* EBIU_SDBCTL Masks */
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H A D | cdefBF561.h | 503 #define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL) 504 #define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/ |
H A D | cdefBF538.h | 484 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 485 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
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H A D | defBF539.h | 191 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro 2217 /* EBIU_SDBCTL Masks */
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H A D | cdefBF538.h | 484 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 485 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
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