Searched refs:EBIU_RSTCTL (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-common/
H A Ddpmc_modes.S177 #if defined(EBIU_RSTCTL) /* DDR */
178 P0.H = hi(EBIU_RSTCTL);
179 P0.L = lo(EBIU_RSTCTL);
215 #if defined(EBIU_RSTCTL) /* DDR */
216 P0.H = hi(EBIU_RSTCTL);
217 P0.L = lo(EBIU_RSTCTL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Ddpmc_modes.S177 #if defined(EBIU_RSTCTL) /* DDR */
178 P0.H = hi(EBIU_RSTCTL);
179 P0.L = lo(EBIU_RSTCTL);
215 #if defined(EBIU_RSTCTL) /* DDR */
216 P0.H = hi(EBIU_RSTCTL);
217 P0.L = lo(EBIU_RSTCTL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h169 #define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */ macro
1780 /* Bit masks for EBIU_RSTCTL */
H A DcdefBF54x_base.h246 #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
247 #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h169 #define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */ macro
1780 /* Bit masks for EBIU_RSTCTL */
H A DcdefBF54x_base.h246 #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
247 #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)

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