Searched refs:DMAC1_TC_PER (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/
H A DdefBF539.h499 #define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ macro
503 #define DMA1_TCPER DMAC1_TC_PER
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DdefBF539.h499 #define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ macro
503 #define DMA1_TCPER DMAC1_TC_PER
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h691 #define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ macro
H A DcdefBF54x_base.h1158 #define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
1159 #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h691 #define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ macro
H A DcdefBF54x_base.h1158 #define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
1159 #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)

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