Searched refs:DDRClock (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-bcmring/csp/chipc/
H A DchipcHw.c100 pPLLReg = &pChipcHw->DDRClock;
310 pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
314 pPLLReg = &pChipcHw->DDRClock;
429 if (pPLLReg == &pChipcHw->DDRClock) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-bcmring/csp/chipc/
H A DchipcHw.c100 pPLLReg = &pChipcHw->DDRClock;
310 pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
314 pPLLReg = &pChipcHw->DDRClock;
429 if (pPLLReg == &pChipcHw->DDRClock) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-bcmring/include/mach/csp/
H A DchipcHw_reg.h34 uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */ member in struct:__anon11758
H A DchipcHw_inline.h849 pPLLReg = &pChipcHw->DDRClock;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-bcmring/include/mach/csp/
H A DchipcHw_reg.h34 uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */ member in struct:__anon23451
H A DchipcHw_inline.h849 pPLLReg = &pChipcHw->DDRClock;

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