/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sparc/kernel/ |
H A D | cpu.c | 46 #define CPU(ver, _name) \ macro 60 CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"), 62 CPU(4, "Fujitsu MB86904"), 63 CPU(5, "Fujitsu TurboSparc MB86907"), 64 CPU(-1, NULL) 80 CPU(0, "LSI Logic Corporation - L64811"), 82 CPU(1, "Cypress/ROSS CY7C601"), 84 CPU(3, "Cypress/ROSS CY7C611"), 86 CPU(0xf, "ROSS HyperSparc RT620"), 87 CPU( [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sparc/kernel/ |
H A D | cpu.c | 46 #define CPU(ver, _name) \ macro 60 CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"), 62 CPU(4, "Fujitsu MB86904"), 63 CPU(5, "Fujitsu TurboSparc MB86907"), 64 CPU(-1, NULL) 80 CPU(0, "LSI Logic Corporation - L64811"), 82 CPU(1, "Cypress/ROSS CY7C601"), 84 CPU(3, "Cypress/ROSS CY7C611"), 86 CPU(0xf, "ROSS HyperSparc RT620"), 87 CPU( [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/sh64/ |
H A D | cpu.h | 0 /* CPU family header for sh64. 34 /* CPU state information. */ 40 #define GET_H_PC() CPU (h_pc) 44 CPU (h_ism) = ANDDI ((x), 1);\ 45 CPU (h_pc) = ANDDI ((x), INVDI (1));\ 50 #define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index]))) 54 CPU (h_gr[(index)]) = (x);\ 61 #define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index]))) 65 CPU (h_s [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/sh64/ |
H A D | cpu.h | 0 /* CPU family header for sh64. 34 /* CPU state information. */ 40 #define GET_H_PC() CPU (h_pc) 44 CPU (h_ism) = ANDDI ((x), 1);\ 45 CPU (h_pc) = ANDDI ((x), INVDI (1));\ 50 #define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index]))) 54 CPU (h_gr[(index)]) = (x);\ 61 #define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index]))) 65 CPU (h_s [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/sh64/ |
H A D | cpu.h | 0 /* CPU family header for sh64. 34 /* CPU state information. */ 40 #define GET_H_PC() CPU (h_pc) 44 CPU (h_ism) = ANDDI ((x), 1);\ 45 CPU (h_pc) = ANDDI ((x), INVDI (1));\ 50 #define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index]))) 54 CPU (h_gr[(index)]) = (x);\ 61 #define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index]))) 65 CPU (h_s [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/m32r/ |
H A D | m32r2.c | 53 return (((CPU (h_bpsw) & 0xc1) << 8) 54 | ((CPU (h_psw) & 0xc0) << 0) 57 return CPU (h_bbpsw) & 0xc1; 62 return CPU (h_gr[H_GR_SP]); 64 return CPU (h_cr[H_CR_SPI]); 67 return CPU (h_gr[H_GR_SP]); 69 return CPU (h_cr[H_CR_SPU]); 71 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 73 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 76 return CPU (h_c [all...] |
H A D | m32rx.c | 53 return (((CPU (h_bpsw) & 0xc1) << 8) 54 | ((CPU (h_psw) & 0xc0) << 0) 57 return CPU (h_bbpsw) & 0xc1; 62 return CPU (h_gr[H_GR_SP]); 64 return CPU (h_cr[H_CR_SPI]); 67 return CPU (h_gr[H_GR_SP]); 69 return CPU (h_cr[H_CR_SPU]); 71 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 73 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 76 return CPU (h_c [all...] |
H A D | cpu.c | 1 /* Misc. support for CPU family m32rbf. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 99 return CPU (h_cond); 107 CPU (h_cond) = newval; 131 return CPU (h_bpsw); 139 CPU (h_bpsw) = newval; 147 return CPU (h_bbps [all...] |
H A D | cpu2.c | 1 /* Misc. support for CPU family m32r2f. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 115 return CPU (h_cond); 123 CPU (h_cond) = newval; 147 return CPU (h_bpsw); 155 CPU (h_bpsw) = newval; 163 return CPU (h_bbps [all...] |
H A D | cpux.c | 1 /* Misc. support for CPU family m32rxf. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 115 return CPU (h_cond); 123 CPU (h_cond) = newval; 147 return CPU (h_bpsw); 155 CPU (h_bpsw) = newval; 163 return CPU (h_bbps [all...] |
H A D | m32r.c | 134 return (((CPU (h_bpsw) & 0xc1) << 8) 135 | ((CPU (h_psw) & 0xc0) << 0) 138 return CPU (h_bbpsw) & 0xc1; 143 return CPU (h_gr[H_GR_SP]); 145 return CPU (h_cr[H_CR_SPI]); 148 return CPU (h_gr[H_GR_SP]); 150 return CPU (h_cr[H_CR_SPU]); 152 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 154 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 157 return CPU (h_c [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/m32r/ |
H A D | m32r2.c | 53 return (((CPU (h_bpsw) & 0xc1) << 8) 54 | ((CPU (h_psw) & 0xc0) << 0) 57 return CPU (h_bbpsw) & 0xc1; 62 return CPU (h_gr[H_GR_SP]); 64 return CPU (h_cr[H_CR_SPI]); 67 return CPU (h_gr[H_GR_SP]); 69 return CPU (h_cr[H_CR_SPU]); 71 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 73 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 76 return CPU (h_c [all...] |
H A D | m32rx.c | 53 return (((CPU (h_bpsw) & 0xc1) << 8) 54 | ((CPU (h_psw) & 0xc0) << 0) 57 return CPU (h_bbpsw) & 0xc1; 62 return CPU (h_gr[H_GR_SP]); 64 return CPU (h_cr[H_CR_SPI]); 67 return CPU (h_gr[H_GR_SP]); 69 return CPU (h_cr[H_CR_SPU]); 71 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 73 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 76 return CPU (h_c [all...] |
H A D | cpu.c | 1 /* Misc. support for CPU family m32rbf. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 99 return CPU (h_cond); 107 CPU (h_cond) = newval; 131 return CPU (h_bpsw); 139 CPU (h_bpsw) = newval; 147 return CPU (h_bbps [all...] |
H A D | cpu2.c | 1 /* Misc. support for CPU family m32r2f. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 115 return CPU (h_cond); 123 CPU (h_cond) = newval; 147 return CPU (h_bpsw); 155 CPU (h_bpsw) = newval; 163 return CPU (h_bbps [all...] |
H A D | cpux.c | 1 /* Misc. support for CPU family m32rxf. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 115 return CPU (h_cond); 123 CPU (h_cond) = newval; 147 return CPU (h_bpsw); 155 CPU (h_bpsw) = newval; 163 return CPU (h_bbps [all...] |
H A D | m32r.c | 134 return (((CPU (h_bpsw) & 0xc1) << 8) 135 | ((CPU (h_psw) & 0xc0) << 0) 138 return CPU (h_bbpsw) & 0xc1; 143 return CPU (h_gr[H_GR_SP]); 145 return CPU (h_cr[H_CR_SPI]); 148 return CPU (h_gr[H_GR_SP]); 150 return CPU (h_cr[H_CR_SPU]); 152 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 154 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 157 return CPU (h_c [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/m32r/ |
H A D | m32r2.c | 53 return (((CPU (h_bpsw) & 0xc1) << 8) 54 | ((CPU (h_psw) & 0xc0) << 0) 57 return CPU (h_bbpsw) & 0xc1; 62 return CPU (h_gr[H_GR_SP]); 64 return CPU (h_cr[H_CR_SPI]); 67 return CPU (h_gr[H_GR_SP]); 69 return CPU (h_cr[H_CR_SPU]); 71 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 73 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 76 return CPU (h_c [all...] |
H A D | m32rx.c | 53 return (((CPU (h_bpsw) & 0xc1) << 8) 54 | ((CPU (h_psw) & 0xc0) << 0) 57 return CPU (h_bbpsw) & 0xc1; 62 return CPU (h_gr[H_GR_SP]); 64 return CPU (h_cr[H_CR_SPI]); 67 return CPU (h_gr[H_GR_SP]); 69 return CPU (h_cr[H_CR_SPU]); 71 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 73 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 76 return CPU (h_c [all...] |
H A D | cpu.c | 1 /* Misc. support for CPU family m32rbf. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 99 return CPU (h_cond); 107 CPU (h_cond) = newval; 131 return CPU (h_bpsw); 139 CPU (h_bpsw) = newval; 147 return CPU (h_bbps [all...] |
H A D | cpu2.c | 1 /* Misc. support for CPU family m32r2f. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 115 return CPU (h_cond); 123 CPU (h_cond) = newval; 147 return CPU (h_bpsw); 155 CPU (h_bpsw) = newval; 163 return CPU (h_bbps [all...] |
H A D | cpux.c | 1 /* Misc. support for CPU family m32rxf. 35 return CPU (h_pc); 43 CPU (h_pc) = newval; 51 return CPU (h_gr[regno]); 59 CPU (h_gr[regno]) = newval; 115 return CPU (h_cond); 123 CPU (h_cond) = newval; 147 return CPU (h_bpsw); 155 CPU (h_bpsw) = newval; 163 return CPU (h_bbps [all...] |
H A D | m32r.c | 134 return (((CPU (h_bpsw) & 0xc1) << 8) 135 | ((CPU (h_psw) & 0xc0) << 0) 138 return CPU (h_bbpsw) & 0xc1; 143 return CPU (h_gr[H_GR_SP]); 145 return CPU (h_cr[H_CR_SPI]); 148 return CPU (h_gr[H_GR_SP]); 150 return CPU (h_cr[H_CR_SPU]); 152 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; 154 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; 157 return CPU (h_c [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/mips/ |
H A D | m16run.c | 28 #define CPU cpu macro 68 CIA_SET (CPU, cia); 70 cia = CIA_GET (CPU);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/mips/ |
H A D | m16run.c | 28 #define CPU cpu macro 68 CIA_SET (CPU, cia); 70 cia = CIA_GET (CPU);
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