/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7366.c | 195 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 199 CLKDEV_CON_ID("rclk", &r_clk), 200 CLKDEV_CON_ID("extal", &extal_clk), 201 CLKDEV_CON_ID("dll_clk", &dll_clk), 202 CLKDEV_CON_ID("pll_clk", &pll_clk), 205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 206 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 208 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 209 CLKDEV_CON_ID("b3_cl [all...] |
H A D | clock-sh7722.c | 178 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 182 CLKDEV_CON_ID("rclk", &r_clk), 183 CLKDEV_CON_ID("extal", &extal_clk), 184 CLKDEV_CON_ID("dll_clk", &dll_clk), 185 CLKDEV_CON_ID("pll_clk", &pll_clk), 188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 189 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 190 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 191 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 192 CLKDEV_CON_ID("b3_cl [all...] |
H A D | clock-sh7724.c | 224 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 228 CLKDEV_CON_ID("rclk", &r_clk), 229 CLKDEV_CON_ID("extal", &extal_clk), 230 CLKDEV_CON_ID("fll_clk", &fll_clk), 231 CLKDEV_CON_ID("pll_clk", &pll_clk), 232 CLKDEV_CON_ID("div3_clk", &div3_clk), 235 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 236 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 237 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 238 CLKDEV_CON_ID("peripheral_cl [all...] |
H A D | clock-sh7723.c | 203 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 207 CLKDEV_CON_ID("rclk", &r_clk), 208 CLKDEV_CON_ID("extal", &extal_clk), 209 CLKDEV_CON_ID("dll_clk", &dll_clk), 210 CLKDEV_CON_ID("pll_clk", &pll_clk), 213 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 214 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 215 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 216 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 217 CLKDEV_CON_ID("b3_cl [all...] |
H A D | clock-sh7343.c | 197 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 201 CLKDEV_CON_ID("rclk", &r_clk), 202 CLKDEV_CON_ID("extal", &extal_clk), 203 CLKDEV_CON_ID("dll_clk", &dll_clk), 204 CLKDEV_CON_ID("pll_clk", &pll_clk), 207 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 208 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 209 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 210 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 211 CLKDEV_CON_ID("b3_cl [all...] |
H A D | clock-sh7786.c | 128 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 132 CLKDEV_CON_ID("extal", &extal_clk), 133 CLKDEV_CON_ID("pll_clk", &pll_clk), 136 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 137 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), 138 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), 139 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 140 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 141 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 175 CLKDEV_CON_ID("ssi3_fc [all...] |
H A D | clock-sh7785.c | 119 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 123 CLKDEV_CON_ID("extal", &extal_clk), 124 CLKDEV_CON_ID("pll_clk", &pll_clk), 127 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 128 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), 129 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]), 130 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), 131 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 132 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 133 CLKDEV_CON_ID("umem_cl [all...] |
H A D | clock-sh7763.c | 94 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 98 CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7366.c | 195 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 199 CLKDEV_CON_ID("rclk", &r_clk), 200 CLKDEV_CON_ID("extal", &extal_clk), 201 CLKDEV_CON_ID("dll_clk", &dll_clk), 202 CLKDEV_CON_ID("pll_clk", &pll_clk), 205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 206 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 208 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 209 CLKDEV_CON_ID("b3_cl [all...] |
H A D | clock-sh7722.c | 178 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 182 CLKDEV_CON_ID("rclk", &r_clk), 183 CLKDEV_CON_ID("extal", &extal_clk), 184 CLKDEV_CON_ID("dll_clk", &dll_clk), 185 CLKDEV_CON_ID("pll_clk", &pll_clk), 188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 189 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 190 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 191 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 192 CLKDEV_CON_ID("b3_cl [all...] |
H A D | clock-sh7724.c | 224 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 228 CLKDEV_CON_ID("rclk", &r_clk), 229 CLKDEV_CON_ID("extal", &extal_clk), 230 CLKDEV_CON_ID("fll_clk", &fll_clk), 231 CLKDEV_CON_ID("pll_clk", &pll_clk), 232 CLKDEV_CON_ID("div3_clk", &div3_clk), 235 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 236 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 237 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 238 CLKDEV_CON_ID("peripheral_cl [all...] |
H A D | clock-sh7723.c | 203 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 207 CLKDEV_CON_ID("rclk", &r_clk), 208 CLKDEV_CON_ID("extal", &extal_clk), 209 CLKDEV_CON_ID("dll_clk", &dll_clk), 210 CLKDEV_CON_ID("pll_clk", &pll_clk), 213 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 214 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 215 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 216 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 217 CLKDEV_CON_ID("b3_cl [all...] |
H A D | clock-sh7343.c | 197 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 201 CLKDEV_CON_ID("rclk", &r_clk), 202 CLKDEV_CON_ID("extal", &extal_clk), 203 CLKDEV_CON_ID("dll_clk", &dll_clk), 204 CLKDEV_CON_ID("pll_clk", &pll_clk), 207 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 208 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 209 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 210 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 211 CLKDEV_CON_ID("b3_cl [all...] |
H A D | clock-sh7786.c | 128 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 132 CLKDEV_CON_ID("extal", &extal_clk), 133 CLKDEV_CON_ID("pll_clk", &pll_clk), 136 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 137 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), 138 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), 139 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 140 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 141 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 175 CLKDEV_CON_ID("ssi3_fc [all...] |
H A D | clock-sh7785.c | 119 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 123 CLKDEV_CON_ID("extal", &extal_clk), 124 CLKDEV_CON_ID("pll_clk", &pll_clk), 127 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 128 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), 129 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]), 130 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), 131 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 132 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 133 CLKDEV_CON_ID("umem_cl [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-shmobile/ |
H A D | clock-sh7377.c | 270 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 275 CLKDEV_CON_ID("r_clk", &r_clk), 276 CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk), 277 CLKDEV_CON_ID("extal2", &sh7377_extal2_clk), 278 CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk), 279 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), 280 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk), 281 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), 282 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), 283 CLKDEV_CON_ID("pllc2_cl [all...] |
H A D | clock-sh7367.c | 262 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 267 CLKDEV_CON_ID("r_clk", &r_clk), 268 CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk), 269 CLKDEV_CON_ID("extal2", &sh7367_extal2_clk), 270 CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk), 271 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), 272 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), 273 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), 274 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), 277 CLKDEV_CON_ID("i_cl [all...] |
H A D | clock-sh7372.c | 446 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 451 CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk), 452 CLKDEV_CON_ID("r_clk", &r_clk), 453 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk), 454 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk), 455 CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk), 456 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), 457 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk), 458 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), 459 CLKDEV_CON_ID("pllc1_cl [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-shmobile/ |
H A D | clock-sh7377.c | 270 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 275 CLKDEV_CON_ID("r_clk", &r_clk), 276 CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk), 277 CLKDEV_CON_ID("extal2", &sh7377_extal2_clk), 278 CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk), 279 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), 280 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk), 281 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), 282 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), 283 CLKDEV_CON_ID("pllc2_cl [all...] |
H A D | clock-sh7367.c | 262 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 267 CLKDEV_CON_ID("r_clk", &r_clk), 268 CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk), 269 CLKDEV_CON_ID("extal2", &sh7367_extal2_clk), 270 CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk), 271 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), 272 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), 273 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), 274 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), 277 CLKDEV_CON_ID("i_cl [all...] |
H A D | clock-sh7372.c | 446 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 451 CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk), 452 CLKDEV_CON_ID("r_clk", &r_clk), 453 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk), 454 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk), 455 CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk), 456 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), 457 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk), 458 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), 459 CLKDEV_CON_ID("pllc1_cl [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/kernel/cpu/ |
H A D | clock-cpg.c | 38 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 42 CLKDEV_CON_ID("master_clk", &master_clk), 43 CLKDEV_CON_ID("peripheral_clk", &peripheral_clk), 44 CLKDEV_CON_ID("bus_clk", &bus_clk), 45 CLKDEV_CON_ID("cpu_clk", &cpu_clk),
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/kernel/cpu/ |
H A D | clock-cpg.c | 38 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 42 CLKDEV_CON_ID("master_clk", &master_clk), 43 CLKDEV_CON_ID("peripheral_clk", &peripheral_clk), 44 CLKDEV_CON_ID("bus_clk", &bus_clk), 45 CLKDEV_CON_ID("cpu_clk", &cpu_clk),
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4/ |
H A D | clock-sh4-202.c | 151 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 155 CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk), 156 CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk), 157 CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/kernel/cpu/sh4/ |
H A D | clock-sh4-202.c | 151 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } macro 155 CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk), 156 CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk), 157 CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
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