/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/lzma-loader/ |
H A D | head.S | 14 #define C0_TAGHI $29 define 106 mtc0 zero,C0_TAGHI,2 113 mtc0 zero,C0_TAGHI 159 mtc0 zero,C0_TAGHI
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/lzma-loader/ |
H A D | head.S | 14 #define C0_TAGHI $29 define 106 mtc0 zero,C0_TAGHI,2 113 mtc0 zero,C0_TAGHI 159 mtc0 zero,C0_TAGHI
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/lzma-loader/ |
H A D | head.S | 14 #define C0_TAGHI $29 define 106 mtc0 zero,C0_TAGHI,2 113 mtc0 zero,C0_TAGHI 159 mtc0 zero,C0_TAGHI
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/src/ |
H A D | rm7000_l1cache.S | 99 dmtc0 zero,C0_TAGHI 111 dmtc0 zero,C0_TAGHI,2
|
H A D | rm7000_l2cache.S | 98 dmtc0 zero,C0_TAGHI 110 dmtc0 zero,C0_TAGHI,2
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/src/ |
H A D | bcmcore_l1cache.S | 104 mtc0 zero,C0_TAGHI 171 mtc0 zero,C0_TAGHI,2 176 mtc0 zero,C0_TAGHI 269 mtc0 zero,C0_TAGHI 353 mtc0 zero,C0_TAGHI
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/src/ |
H A D | sb1250_l1cache.S | 94 * CP0 C0_TAGHI values for cache freezing/way elimination 275 dmtc0 zero,C0_TAGHI 277 dmtc0 zero,C0_TAGHI,2 346 dmtc0 t1,C0_TAGHI,2 348 dmtc0 t1,C0_TAGHI 419 dmtc0 zero,C0_TAGHI 435 dmtc0 zero,C0_TAGHI,2
|
H A D | diag_l2cache.S | 78 #define C0_DataHi C0_TAGHI 80 #define C0_TagHi C0_TAGHI
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/ |
H A D | sbmips.h | 242 #define C0_TAGHI $29 /* CP0: TagHi */ macro 276 #define C0_TAGHI 29 /* CP0: TagHi */ macro 535 _cp0_get_reg_u64 (taghi_i, C0_TAGHI, 0) 536 _cp0_set_reg_u64 (taghi_i, C0_TAGHI, 0) 539 _cp0_get_reg_u64 (datahi_i, C0_TAGHI, 1) 542 _cp0_get_reg_u64 (taghi_d, C0_TAGHI, 2) 543 _cp0_set_reg_u64 (taghi_d, C0_TAGHI, 2) 546 _cp0_get_reg_u64 (datahi_d, C0_TAGHI, 3)
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/shared/ |
H A D | min_osl.c | 93 MTC0(C0_TAGHI, 0, 0); 105 MTC0(C0_TAGHI, 2, 0); 108 MTC0(C0_TAGHI, 0, 0);
|
H A D | boot.S | 377 mtc0 zero,C0_TAGHI,2 383 mtc0 zero,C0_TAGHI 426 mtc0 zero,C0_TAGHI
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/include/ |
H A D | mipsinc.h | 101 #define C0_TAGHI $29 macro 179 #define C0_TAGHI 29 /* CP0: TagHi */ macro
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/include/ |
H A D | sbmips.h | 233 #define C0_TAGHI $29 /* CP0: TagHi */ macro 262 #define C0_TAGHI 29 /* CP0: TagHi */ macro
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm5200/include/ |
H A D | r5kc0.h | 343 #define C0_TAGHI $29 macro 459 #define C0_TAGHI 29 macro
|
H A D | sbmips.h | 232 #define C0_TAGHI $29 /* CP0: TagHi */ macro 260 #define C0_TAGHI 29 /* CP0: TagHi */ macro
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/include/ |
H A D | r5kc0.h | 344 #define C0_TAGHI $29 macro 460 #define C0_TAGHI 29 macro
|
H A D | sbmips.h | 232 #define C0_TAGHI $29 /* CP0: TagHi */ macro 260 #define C0_TAGHI 29 /* CP0: TagHi */ macro
|
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/verif/ |
H A D | vapi.S | 409 LSAVECP0(C0_TAGHI,55) 778 SAVECP0(C0_TAGHI,55)
|