Searched refs:C0_TAGHI (Results 1 - 18 of 18) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/lzma-loader/
H A Dhead.S14 #define C0_TAGHI $29 define
106 mtc0 zero,C0_TAGHI,2
113 mtc0 zero,C0_TAGHI
159 mtc0 zero,C0_TAGHI
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/lzma-loader/
H A Dhead.S14 #define C0_TAGHI $29 define
106 mtc0 zero,C0_TAGHI,2
113 mtc0 zero,C0_TAGHI
159 mtc0 zero,C0_TAGHI
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/lzma-loader/
H A Dhead.S14 #define C0_TAGHI $29 define
106 mtc0 zero,C0_TAGHI,2
113 mtc0 zero,C0_TAGHI
159 mtc0 zero,C0_TAGHI
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/src/
H A Drm7000_l1cache.S99 dmtc0 zero,C0_TAGHI
111 dmtc0 zero,C0_TAGHI,2
H A Drm7000_l2cache.S98 dmtc0 zero,C0_TAGHI
110 dmtc0 zero,C0_TAGHI,2
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/src/
H A Dbcmcore_l1cache.S104 mtc0 zero,C0_TAGHI
171 mtc0 zero,C0_TAGHI,2
176 mtc0 zero,C0_TAGHI
269 mtc0 zero,C0_TAGHI
353 mtc0 zero,C0_TAGHI
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/src/
H A Dsb1250_l1cache.S94 * CP0 C0_TAGHI values for cache freezing/way elimination
275 dmtc0 zero,C0_TAGHI
277 dmtc0 zero,C0_TAGHI,2
346 dmtc0 t1,C0_TAGHI,2
348 dmtc0 t1,C0_TAGHI
419 dmtc0 zero,C0_TAGHI
435 dmtc0 zero,C0_TAGHI,2
H A Ddiag_l2cache.S78 #define C0_DataHi C0_TAGHI
80 #define C0_TagHi C0_TAGHI
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/
H A Dsbmips.h242 #define C0_TAGHI $29 /* CP0: TagHi */ macro
276 #define C0_TAGHI 29 /* CP0: TagHi */ macro
535 _cp0_get_reg_u64 (taghi_i, C0_TAGHI, 0)
536 _cp0_set_reg_u64 (taghi_i, C0_TAGHI, 0)
539 _cp0_get_reg_u64 (datahi_i, C0_TAGHI, 1)
542 _cp0_get_reg_u64 (taghi_d, C0_TAGHI, 2)
543 _cp0_set_reg_u64 (taghi_d, C0_TAGHI, 2)
546 _cp0_get_reg_u64 (datahi_d, C0_TAGHI, 3)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/shared/
H A Dmin_osl.c93 MTC0(C0_TAGHI, 0, 0);
105 MTC0(C0_TAGHI, 2, 0);
108 MTC0(C0_TAGHI, 0, 0);
H A Dboot.S377 mtc0 zero,C0_TAGHI,2
383 mtc0 zero,C0_TAGHI
426 mtc0 zero,C0_TAGHI
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/include/
H A Dmipsinc.h101 #define C0_TAGHI $29 macro
179 #define C0_TAGHI 29 /* CP0: TagHi */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/include/
H A Dsbmips.h233 #define C0_TAGHI $29 /* CP0: TagHi */ macro
262 #define C0_TAGHI 29 /* CP0: TagHi */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm5200/include/
H A Dr5kc0.h343 #define C0_TAGHI $29 macro
459 #define C0_TAGHI 29 macro
H A Dsbmips.h232 #define C0_TAGHI $29 /* CP0: TagHi */ macro
260 #define C0_TAGHI 29 /* CP0: TagHi */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/include/
H A Dr5kc0.h344 #define C0_TAGHI $29 macro
460 #define C0_TAGHI 29 macro
H A Dsbmips.h232 #define C0_TAGHI $29 /* CP0: TagHi */ macro
260 #define C0_TAGHI 29 /* CP0: TagHi */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/verif/
H A Dvapi.S409 LSAVECP0(C0_TAGHI,55)
778 SAVECP0(C0_TAGHI,55)

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