Searched refs:BIT_16 (Results 1 - 15 of 15) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/bcm57xx/sys/
H A Dbits.h41 #define BIT_16 0x010000 macro
H A Dtigon3.h153 #define T3_SHASTA_EXT_LED_MODE_MASK (BIT_15 | BIT_16)
156 #define T3_SHASTA_EXT_LED_MAC_MODE BIT_16
157 #define T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE (BIT_15 | BIT_16)
1483 #define DMA_CTRL_PCIX_READ_WATERMARK_MASK (BIT_18 | BIT_17 | BIT_16)
1485 #define DMA_CTRL_PCIX_READ_WATERMARK_128 (BIT_16)
1487 #define DMA_CTRL_PCIX_READ_WATERMARK_384 (BIT_17 | BIT_16)
1489 #define DMA_CTRL_PCIX_READ_WATERMARK_1024 (BIT_18 | BIT_16)
1491 #define DMA_CTRL_PCIX_READ_WATERMARK_1536 (BIT_18 | BIT_17 | BIT_16)
1613 #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16
2399 #define DMA_READ_MODE_FIFO_LONG_BURST (BIT_16 | BIT_1
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H A Dtigon3.c8974 REG_WR_OFFSET(pDevice, 0x7d00,Value32 & ~(BIT_16 | BIT_4 | BIT_2 | BIT_1 | BIT_0));
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/qla2xxx/
H A Dqla_fw.h906 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
984 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
986 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1000 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1002 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
H A Dqla_sup.c1755 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1759 } else if (((addr & BIT_16) == 0) &&
1816 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1820 } else if (((addr & BIT_16) == 0) &&
H A Dqla_def.h74 #define BIT_16 0x10000 macro
728 #define MBX_16 BIT_16
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/qla2xxx/
H A Dqla_fw.h906 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
984 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
986 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1000 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1002 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
H A Dqla_sup.c1755 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1759 } else if (((addr & BIT_16) == 0) &&
1816 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1820 } else if (((addr & BIT_16) == 0) &&
H A Dqla_def.h74 #define BIT_16 0x10000 macro
728 #define MBX_16 BIT_16
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/qla4xxx/
H A Dql4_def.h95 #define BIT_16 0x10000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/qla4xxx/
H A Dql4_def.h95 #define BIT_16 0x10000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/qlcnic/
H A Dqlcnic_hdr.h227 #define BIT_16 0x10000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/
H A Dqla1280.h42 #define BIT_16 0x10000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/
H A Dqla1280.h42 #define BIT_16 0x10000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/qlcnic/
H A Dqlcnic_hdr.h227 #define BIT_16 0x10000 macro

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