Searched refs:BIT_15 (Results 1 - 23 of 23) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/bcm57xx/sys/
H A Dbits.h40 #define BIT_15 0x8000 macro
H A Dtigon3.h106 #define T3_NIC_BOTH_PORT_100MB_WOL_CAPABLE BIT_15
153 #define T3_SHASTA_EXT_LED_MODE_MASK (BIT_15 | BIT_16)
155 #define T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE BIT_15
157 #define T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE (BIT_15 | BIT_16)
494 #define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15
521 #define T3_PM_PME_ASSERTED BIT_15
608 #define PHY_CTRL_PHY_RESET BIT_15
725 #define BCM540X_EXT_CTRL_TBI BIT_15
774 #define BCM540X_CONTROL_ALL_CHANNELS BIT_15
807 #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15
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H A Dtigon3.c3699 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | BIT_15);
8416 LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/qla2xxx/
H A Dqla_fw.h658 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
907 #define CSRX_FUNCTION BIT_15 /* Function number. */
954 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
1385 #define VCO_ENABLE_DSD BIT_15
1494 #define FAC_OPT_FORCE_SEMAPHORE BIT_15
H A Dqla_def.h73 #define BIT_15 0x8000 macro
302 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
311 #define NVR_BUSY BIT_15
343 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
729 #define MBX_15 BIT_15
1439 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
H A Dqla_nx.h858 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
H A Dqla_mbx.c2568 mcp->mb[2] = sw_em_1g | BIT_15;
2569 mcp->mb[3] = sw_em_2g | BIT_15;
2570 mcp->mb[4] = sw_em_4g | BIT_15;
3851 mcp->mb[1] |= BIT_15;
H A Dqla_gs.c1877 case BIT_15:
H A Dqla_isr.c162 if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
H A Dqla_init.c4350 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5116 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/qla2xxx/
H A Dqla_fw.h658 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
907 #define CSRX_FUNCTION BIT_15 /* Function number. */
954 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
1385 #define VCO_ENABLE_DSD BIT_15
1494 #define FAC_OPT_FORCE_SEMAPHORE BIT_15
H A Dqla_def.h73 #define BIT_15 0x8000 macro
302 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
311 #define NVR_BUSY BIT_15
343 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
729 #define MBX_15 BIT_15
1439 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
H A Dqla_nx.h858 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
H A Dqla_mbx.c2568 mcp->mb[2] = sw_em_1g | BIT_15;
2569 mcp->mb[3] = sw_em_2g | BIT_15;
2570 mcp->mb[4] = sw_em_4g | BIT_15;
3851 mcp->mb[1] |= BIT_15;
H A Dqla_gs.c1877 case BIT_15:
H A Dqla_isr.c162 if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
H A Dqla_init.c4350 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5116 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/
H A Dqla1280.h41 #define BIT_15 0x8000 macro
327 #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */
979 #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/
H A Dqla1280.h41 #define BIT_15 0x8000 macro
327 #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */
979 #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/qla4xxx/
H A Dql4_def.h94 #define BIT_15 0x8000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/qla4xxx/
H A Dql4_def.h94 #define BIT_15 0x8000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/qlcnic/
H A Dqlcnic_hdr.h226 #define BIT_15 0x8000 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/qlcnic/
H A Dqlcnic_hdr.h226 #define BIT_15 0x8000 macro

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