Searched refs:lobj (Results 1 - 25 of 115) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/radeon/
H A Dradeon_object.c291 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, argument
294 if (lobj->wdomain) {
295 list_add(&lobj->list, head);
297 list_add_tail(&lobj->list, head);
303 struct radeon_bo_list *lobj; local
306 list_for_each_entry(lobj, head, list){
307 r = radeon_bo_reserve(lobj->bo, false);
310 lobj->reserved = true;
317 struct radeon_bo_list *lobj; local
319 list_for_each_entry(lobj, hea
328 struct radeon_bo_list *lobj; local
365 struct radeon_bo_list *lobj; local
[all...]
H A Devergreen_cs.c484 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
510 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
521 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
532 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
543 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
596 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
599 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
616 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
619 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
711 ib[idx] += (u32)((reloc->lobj
[all...]
H A Dr100_track.h118 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
120 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
122 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
160 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
172 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
186 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
H A Dr200.c185 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
197 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
213 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
256 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
271 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
273 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
339 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
H A Dr600_cs.c534 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
535 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
787 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
836 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
839 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
891 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
917 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
937 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
949 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1012 ib[idx] += (u32)((reloc->lobj
[all...]
H A Dradeon_cs.c78 p->relocs[i].lobj.bo = p->relocs[i].robj;
79 p->relocs[i].lobj.rdomain = r->read_domains;
80 p->relocs[i].lobj.wdomain = r->write_domain;
83 INIT_LIST_HEAD(&p->relocs[i].lobj.list);
84 radeon_bo_list_add_object(&p->relocs[i].lobj,
H A Dr300.c665 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
677 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
704 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
706 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
708 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
711 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
762 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
764 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
766 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
835 if (reloc->lobj
[all...]
H A Dradeon_object.h152 extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
H A Dr100.c1415 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1427 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1440 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1457 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1474 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1491 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1506 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1508 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1569 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1723 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/radeon/
H A Dradeon_object.c291 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, argument
294 if (lobj->wdomain) {
295 list_add(&lobj->list, head);
297 list_add_tail(&lobj->list, head);
303 struct radeon_bo_list *lobj; local
306 list_for_each_entry(lobj, head, list){
307 r = radeon_bo_reserve(lobj->bo, false);
310 lobj->reserved = true;
317 struct radeon_bo_list *lobj; local
319 list_for_each_entry(lobj, hea
328 struct radeon_bo_list *lobj; local
365 struct radeon_bo_list *lobj; local
[all...]
H A Devergreen_cs.c484 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
510 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
521 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
532 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
543 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
596 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
599 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
616 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
619 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
711 ib[idx] += (u32)((reloc->lobj
[all...]
H A Dr100_track.h118 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
120 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
122 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
160 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
172 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
186 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
H A Dr200.c185 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
197 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
213 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
256 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
271 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
273 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
339 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
H A Dr600_cs.c534 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
535 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
787 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
836 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
839 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
891 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
917 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
937 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
949 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1012 ib[idx] += (u32)((reloc->lobj
[all...]
H A Dradeon_cs.c78 p->relocs[i].lobj.bo = p->relocs[i].robj;
79 p->relocs[i].lobj.rdomain = r->read_domains;
80 p->relocs[i].lobj.wdomain = r->write_domain;
83 INIT_LIST_HEAD(&p->relocs[i].lobj.list);
84 radeon_bo_list_add_object(&p->relocs[i].lobj,
H A Dr300.c665 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
677 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
704 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
706 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
708 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
711 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
762 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
764 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
766 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
835 if (reloc->lobj
[all...]
H A Dradeon_object.h152 extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
H A Dr100.c1415 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1427 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1440 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1457 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1474 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1491 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1506 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1508 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1569 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1723 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/lzo/autoconf/
H A Dltmain.sh809 lobj=${xdir}$objdir/$objname
819 removelist="$obj $lobj $libobj ${libobj}T"
821 removelist="$lobj $libobj ${libobj}T"
923 command="$command -o $lobj"
926 $run $rm "$lobj" "$output_obj"
956 if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then
957 $show "$mv $output_obj $lobj"
958 if $run $mv $output_obj $lobj; then :
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/accel-pptp/
H A Dltmain.sh853 lobj=${xdir}$objdir/$objname
863 removelist="$obj $lobj $libobj ${libobj}T"
865 removelist="$lobj $libobj ${libobj}T"
967 command="$command -o $lobj"
970 $run $rm "$lobj" "$output_obj"
1000 if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then
1001 $show "$mv $output_obj $lobj"
1002 if $run $mv $output_obj $lobj; then :
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/accel-pptpd/pppd_plugin/
H A Dltmain.sh853 lobj=${xdir}$objdir/$objname
863 removelist="$obj $lobj $libobj ${libobj}T"
865 removelist="$lobj $libobj ${libobj}T"
967 command="$command -o $lobj"
970 $run $rm "$lobj" "$output_obj"
1000 if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then
1001 $show "$mv $output_obj $lobj"
1002 if $run $mv $output_obj $lobj; then :
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/lzo/autoconf/
H A Dltmain.sh809 lobj=${xdir}$objdir/$objname
819 removelist="$obj $lobj $libobj ${libobj}T"
821 removelist="$lobj $libobj ${libobj}T"
923 command="$command -o $lobj"
926 $run $rm "$lobj" "$output_obj"
956 if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then
957 $show "$mv $output_obj $lobj"
958 if $run $mv $output_obj $lobj; then :
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/accel-pptp/
H A Dltmain.sh853 lobj=${xdir}$objdir/$objname
863 removelist="$obj $lobj $libobj ${libobj}T"
865 removelist="$lobj $libobj ${libobj}T"
967 command="$command -o $lobj"
970 $run $rm "$lobj" "$output_obj"
1000 if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then
1001 $show "$mv $output_obj $lobj"
1002 if $run $mv $output_obj $lobj; then :
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/accel-pptpd/pppd_plugin/
H A Dltmain.sh853 lobj=${xdir}$objdir/$objname
863 removelist="$obj $lobj $libobj ${libobj}T"
865 removelist="$lobj $libobj ${libobj}T"
967 command="$command -o $lobj"
970 $run $rm "$lobj" "$output_obj"
1000 if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then
1001 $show "$mv $output_obj $lobj"
1002 if $run $mv $output_obj $lobj; then :
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/accel-pptp/
H A Dltmain.sh853 lobj=${xdir}$objdir/$objname
863 removelist="$obj $lobj $libobj ${libobj}T"
865 removelist="$lobj $libobj ${libobj}T"
967 command="$command -o $lobj"
970 $run $rm "$lobj" "$output_obj"
1000 if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then
1001 $show "$mv $output_obj $lobj"
1002 if $run $mv $output_obj $lobj; then :

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