1 2#define R100_TRACK_MAX_TEXTURE 3 3#define R200_TRACK_MAX_TEXTURE 6 4#define R300_TRACK_MAX_TEXTURE 16 5 6#define R100_MAX_CB 1 7#define R300_MAX_CB 4 8 9/* 10 * CS functions 11 */ 12struct r100_cs_track_cb { 13 struct radeon_bo *robj; 14 unsigned pitch; 15 unsigned cpp; 16 unsigned offset; 17}; 18 19struct r100_cs_track_array { 20 struct radeon_bo *robj; 21 unsigned esize; 22}; 23 24struct r100_cs_cube_info { 25 struct radeon_bo *robj; 26 unsigned offset; 27 unsigned width; 28 unsigned height; 29}; 30 31#define R100_TRACK_COMP_NONE 0 32#define R100_TRACK_COMP_DXT1 1 33#define R100_TRACK_COMP_DXT35 2 34 35struct r100_cs_track_texture { 36 struct radeon_bo *robj; 37 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 38 unsigned pitch; 39 unsigned width; 40 unsigned height; 41 unsigned num_levels; 42 unsigned cpp; 43 unsigned tex_coord_type; 44 unsigned txdepth; 45 unsigned width_11; 46 unsigned height_11; 47 bool use_pitch; 48 bool enabled; 49 bool lookup_disable; 50 bool roundup_w; 51 bool roundup_h; 52 unsigned compress_format; 53}; 54 55struct r100_cs_track_limits { 56 unsigned num_cb; 57 unsigned num_texture; 58 unsigned max_levels; 59}; 60 61struct r100_cs_track { 62 struct radeon_device *rdev; 63 unsigned num_cb; 64 unsigned num_texture; 65 unsigned maxy; 66 unsigned vtx_size; 67 unsigned vap_vf_cntl; 68 unsigned vap_alt_nverts; 69 unsigned immd_dwords; 70 unsigned num_arrays; 71 unsigned max_indx; 72 unsigned color_channel_mask; 73 struct r100_cs_track_array arrays[11]; 74 struct r100_cs_track_cb cb[R300_MAX_CB]; 75 struct r100_cs_track_cb zb; 76 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 77 bool z_enabled; 78 bool separate_cube; 79 bool zb_cb_clear; 80 bool blend_read_enable; 81}; 82 83int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 84void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 85int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 86 struct radeon_cs_reloc **cs_reloc); 87void r100_cs_dump_packet(struct radeon_cs_parser *p, 88 struct radeon_cs_packet *pkt); 89 90int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 91 92int r200_packet0_check(struct radeon_cs_parser *p, 93 struct radeon_cs_packet *pkt, 94 unsigned idx, unsigned reg); 95 96 97 98static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 99 struct radeon_cs_packet *pkt, 100 unsigned idx, 101 unsigned reg) 102{ 103 int r; 104 u32 tile_flags = 0; 105 u32 tmp; 106 struct radeon_cs_reloc *reloc; 107 u32 value; 108 109 r = r100_cs_packet_next_reloc(p, &reloc); 110 if (r) { 111 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 112 idx, reg); 113 r100_cs_dump_packet(p, pkt); 114 return r; 115 } 116 value = radeon_get_ib_value(p, idx); 117 tmp = value & 0x003fffff; 118 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 119 120 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 121 tile_flags |= RADEON_DST_TILE_MACRO; 122 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 123 if (reg == RADEON_SRC_PITCH_OFFSET) { 124 DRM_ERROR("Cannot src blit from microtiled surface\n"); 125 r100_cs_dump_packet(p, pkt); 126 return -EINVAL; 127 } 128 tile_flags |= RADEON_DST_TILE_MICRO; 129 } 130 131 tmp |= tile_flags; 132 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; 133 return 0; 134} 135 136static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 137 struct radeon_cs_packet *pkt, 138 int idx) 139{ 140 unsigned c, i; 141 struct radeon_cs_reloc *reloc; 142 struct r100_cs_track *track; 143 int r = 0; 144 volatile uint32_t *ib; 145 u32 idx_value; 146 147 ib = p->ib->ptr; 148 track = (struct r100_cs_track *)p->track; 149 c = radeon_get_ib_value(p, idx++) & 0x1F; 150 track->num_arrays = c; 151 for (i = 0; i < (c - 1); i+=2, idx+=3) { 152 r = r100_cs_packet_next_reloc(p, &reloc); 153 if (r) { 154 DRM_ERROR("No reloc for packet3 %d\n", 155 pkt->opcode); 156 r100_cs_dump_packet(p, pkt); 157 return r; 158 } 159 idx_value = radeon_get_ib_value(p, idx); 160 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 161 162 track->arrays[i + 0].esize = idx_value >> 8; 163 track->arrays[i + 0].robj = reloc->robj; 164 track->arrays[i + 0].esize &= 0x7F; 165 r = r100_cs_packet_next_reloc(p, &reloc); 166 if (r) { 167 DRM_ERROR("No reloc for packet3 %d\n", 168 pkt->opcode); 169 r100_cs_dump_packet(p, pkt); 170 return r; 171 } 172 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 173 track->arrays[i + 1].robj = reloc->robj; 174 track->arrays[i + 1].esize = idx_value >> 24; 175 track->arrays[i + 1].esize &= 0x7F; 176 } 177 if (c & 1) { 178 r = r100_cs_packet_next_reloc(p, &reloc); 179 if (r) { 180 DRM_ERROR("No reloc for packet3 %d\n", 181 pkt->opcode); 182 r100_cs_dump_packet(p, pkt); 183 return r; 184 } 185 idx_value = radeon_get_ib_value(p, idx); 186 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 187 track->arrays[i + 0].robj = reloc->robj; 188 track->arrays[i + 0].esize = idx_value >> 8; 189 track->arrays[i + 0].esize &= 0x7F; 190 } 191 return r; 192} 193