| /asus-wl-520gu-7.0.1.45/src/linux/linux/arch/parisc/math-emu/ |
| H A D | dfadd.c | 208 Dbl_setwrapped_exponent(leftp1,result_exponent,unfl);
260 Dbl_setwrapped_exponent(resultp1,result_exponent,unfl);
424 Dbl_setwrapped_exponent(resultp1,result_exponent,unfl);
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| H A D | dfsub.c | 211 Dbl_setwrapped_exponent(leftp1,result_exponent,unfl);
263 Dbl_setwrapped_exponent(resultp1,result_exponent,unfl);
427 Dbl_setwrapped_exponent(resultp1,result_exponent,unfl);
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| H A D | sfadd.c | 208 Sgl_setwrapped_exponent(left,result_exponent,unfl);
257 Sgl_setwrapped_exponent(result,result_exponent,unfl);
419 Sgl_setwrapped_exponent(result,result_exponent,unfl);
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| H A D | sfsub.c | 209 Sgl_setwrapped_exponent(left,result_exponent,unfl);
259 Sgl_setwrapped_exponent(result,result_exponent,unfl);
422 Sgl_setwrapped_exponent(result,result_exponent,unfl);
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| H A D | sfrem.c | 272 Sgl_setwrapped_exponent(result,dest_exponent,unfl);
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| H A D | fmpyfadd.c | 321 unfl);
363 unfl);
696 Dbl_setwrapped_exponent(resultp1,result_exponent,unfl);
981 unfl);
1023 unfl);
1354 Dbl_setwrapped_exponent(resultp1,result_exponent,unfl);
1637 unfl);
1679 unfl);
1995 Sgl_setwrapped_exponent(resultp1,result_exponent,unfl);
2279 unfl);
[all...] |
| H A D | dfrem.c | 278 Dbl_setwrapped_exponent(resultp1,dest_exponent,unfl);
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| H A D | fcnvff.c | 286 Sgl_setwrapped_exponent(result,dest_exponent,unfl);
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| H A D | dfdiv.c | 319 Dbl_setwrapped_exponent(resultp1,dest_exponent,unfl);
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| H A D | dfmpy.c | 314 Dbl_setwrapped_exponent(resultp1,dest_exponent,unfl);
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| H A D | sfdiv.c | 313 Sgl_setwrapped_exponent(result,dest_exponent,unfl);
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| H A D | sfmpy.c | 300 Sgl_setwrapped_exponent(result,dest_exponent,unfl);
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| H A D | sgl_float.h | 194 #define unfl + macro
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| H A D | dbl_float.h | 317 #define unfl + macro
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| /asus-wl-520gu-7.0.1.45/src/linux/linux/arch/m68k/fpsp040/ |
| H A D | skeleton.S | 90 | bug, if an E1 snan, ovfl, or unfl occurred, and the process was
93 | and unfl exception to be taken must not have been enabled. The
95 | or unfl bits set in the fpsr. If any of these are set, branch
125 btstb #unfl_bit,2(%sp) |test for unfl
130 bra unfl
202 .global unfl
203 unfl: label
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| H A D | scale.S | 64 | and set unfl.
133 orl #unfl_bit,USER_FPSR(%a6) |set unfl
169 blt fix_unfl |if lower, catastrophic unfl
187 | ;set unfl, aunfl, ainex
246 orl #unfl_mask,USER_FPSR(%a6) |set unfl
256 | unfl, aunfl, and ainex.
346 orl #unfl_mask,USER_FPSR(%a6) |set unfl
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| H A D | kernel_ex.S | 131 | This entry point is used by all routines requiring unfl, inex2,
273 btstb #unfl_bit,FPSR_EXCEPT(%a6) |test for unfl bit set
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| H A D | x_unfl.S | 82 | unfl. If the inex enable bit is set in the FPCR, and either
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| H A D | gen_except.S | 19 | unfl
361 bfextu USER_FPSR(%a6){#17:#4},%d0 |get snan/operr/ovfl/unfl bits
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| H A D | res_func.S | 333 orl #unfl_mask,USER_FPSR(%a6) |set unfl
528 | Simply set unfl (not inex2 or aunfl) and write the result to
1446 | set if the result is inex and unfl is signalled.
1460 | that gen_except will have a correctly signed value for ovfl/unfl
1478 | that gen_except will have a correctly signed value for ovfl/unfl
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| H A D | bugfix.S | 171 | nu-generated ovfl, unfl, or inex exception. If the version
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| /asus-wl-520gu-7.0.1.45/src/linux/linux/arch/m68k/ifpsp060/src/ |
| H A D | ftest.S | 125 ### unfl non-maskable
199 ### unfl
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| H A D | pfpsp.S | 536 set UNFL_VEC, 0xcc # unfl vector offset
966 # funfl_{unfl,inex}_on() because w/ both exceptions disabled, this
1673 # for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
6872 # can inex1 also be set along with unfl and inex2???
6932 # can inex1 also be set along with unfl and inex2???
8041 cmp.l %d0,(tbl_fmul_unfl.w,%pc,%d1.w*4) # would result unfl?
8042 beq.w fmul_may_unfl # result may rnd to no unfl
8205 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
8527 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
8628 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl ex
[all...] |
| H A D | fpsp.S | 537 set UNFL_VEC, 0xcc # unfl vector offset
967 # funfl_{unfl,inex}_on() because w/ both exceptions disabled, this
1674 # for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
9683 # and set unfl.
10206 # unfl enabled #
10242 bsr.l unf_sub # calc default unfl result
10254 bsr.l unf_sub # calc default unfl result
11610 cmp.l %d0,(tbl_fmul_unfl.w,%pc,%d1.w*4) # would result unfl?
11611 beq.w fmul_may_unfl # result may rnd to no unfl
11774 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl ex
[all...] |
| H A D | fplsp.S | 517 set UNFL_VEC, 0xcc # unfl vector offset
9324 # and set unfl.
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