Searched refs:L1_CACHE_ALIGN (Results 1 - 16 of 16) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-alpha/
H A Dcache.h21 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-arm/
H A Dcache.h8 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-alpha/
H A Dcache.h21 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-arm/
H A Dcache.h8 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/linux/
H A Dcache.h7 #ifndef L1_CACHE_ALIGN
8 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/linux/
H A Dcache.h7 #ifndef L1_CACHE_ALIGN
8 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-sparc64/
H A Dcache.h10 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-sparc64/
H A Dcache.h10 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-parisc/
H A Dcache.h25 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-parisc/
H A Dcache.h25 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-ppc/
H A Dcache.h32 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-ppc/
H A Dcache.h32 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-sparc/
H A Dcache.h14 #define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-sparc/
H A Dcache.h14 #define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/scsi/
H A D53c700.h248 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
250 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
252 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
254 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
256 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
/asus-wl-520gu-7.0.1.45/src/linux/linux/mm/
H A Dslab.c401 while (i*size + L1_CACHE_ALIGN(base+i*extra) <= wastage)
411 wastage -= L1_CACHE_ALIGN(base+i*extra);
760 slab_size = L1_CACHE_ALIGN(cachep->num*sizeof(kmem_bufctl_t)+sizeof(slab_t));
1041 colour_off += L1_CACHE_ALIGN(cachep->num *

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